A 40-to-56Gb/s PAM-4 Receiver with 10-Tap Direct Decision-Feedback Equalization in 16nm FinFET

📋 论文概要

本文提出了一种采用10抽头直接判决反馈均衡（DFE）的PAM-4接收器，工作速率为40至56Gb/s，旨在满足数据中心和电信基础设施对更高带宽的需求。该接收器基于16nm FinFET工艺实现，支持CEI-56G-VSR-PAM4标准。

💡 主要创新点

• 首次在16nm FinFET工艺中实现10抽头直接DFE的PAM-4接收器，支持56Gb/s高速率。
• 通过直接DFE架构有效补偿信道损耗，提升PAM-4信号的接收质量。

🏷 关键词

📄 原文摘要

Adam Chou1, Tim Cronin1, Kevin Geary3, Scott McLeod1, Lei Zhou1, Ian Zhuang1, Jaeduk Han4, Sen Lin4, Parag Upadhyaya1, Geoff Zhang1, Yohan Frans1, Ken Chang1 Xilinx, San Jose, CA Xilinx, Singapore, Singapore 3 Xilinx, Cork, Ireland 4 University of California, Berkeley, CA 1 2 The increasing bandwidth demand in data centers and telecommunication infrastructures had prompted new electrical interface standards capable of operating up to 56Gb/s per-lane. The CEI-56G-VSR-PAM4 standard [1] defines PAM-4 signaling at 56Gb/s targeting chip-to-module interconnect. Figure 6.3.1 shows the measured S21 of a channel resembling such interconnects and the corresponding single-pulse response after TX-FIR and RX CTLE. Although the S21 is merely ~10dB at 14GHz, the single-pulse response exhibits significant reflections from impedance discontinuities, mainly between package and PCB traces. These reflections are detrimental to PAM-4 signaling and cannot be

👥 作者与机构

Jay Im1, Dave Freitas1, Arianne Roldan2, Ronan Casey3, Stanley Chen1,