ISSCC 2017
Session 1
Plenary
A Smart Design Paradigm for Smart Chips Cliff Hou
Industry application trends have seen important usage-model shifts from the PC era to the mobile-computing era, where individuals have moved from possessing one device to multiple devices that connect them to people [1].
ISSCC 2017
Session 1
Plenary
Dynamics of Exponentials in Circuits and Systems
1.1 Introduction Scaling of CMOS, the technology that has driven our industry for 45 years and prompted unprecedented innovations in device, circuit, and manufacturing, is coming to an end. There is no unanimous agreemen
ISSCC 2017
Session 1
Plenary
February 6, 2017 / 10:45 AM The Development of High-Speed DNA Sequencing:
that biological information was encoded in DNA as a sequence of chemical building-block “letters”, developing technology for reading (or “sequencing”) this chemical code has been fundamental to advances in biology and me
ISSCC 2017
Session 1
Plenary
Quantum Computing – The Next Challenge in Circuit and System Design Lieven Vandersypen
1. Overview Quantum computers have the potential to tackle problems in materials science, chemistry, and mathematics that are well beyond the reach of supercomputers. Their power derives from the use of quantum bits, whi
ISSCC 2017
Session 10
Power Management
A 1.1W/mm2-Power-Density 82%-Efficiency Fully Integrated 3:1 Switched-Capacitor DC-DC Converter in Baseline 28nm CMOS Using Stage Outphasing and Multiphase Soft-Charging
Over the past years, delivering power to integrated circuits has become increasingly difficult. With the current intake of many modern-day applications growing each new process generation, the Power Delivery Network (PDN
ISSCC 2017
Session 10
Power Management
A Digitally Controlled 94.8%-Peak-Efficiency Hybrid Switched-Capacitor Converter for Bidirectional Balancing and Impedance-Based Diagnostics of Lithium-Ion Battery Arrays
Intel, Hillsboro, OR 3 Hive Battery, Seattle, WA 1 2 With the growing adoption of electrified transportation and need for active storage in the electrical grid, electrochemical energy storage has become increasingly impo
ISSCC 2017
Session 10
Power Management
A 94.2%-Peak-Efficiency 1.53A Direct-Battery-HookUp Hybrid Dickson Switched-Capacitor DC-DC Converter with Wide Continuous Conversion Ratio in 65nm CMOS
University of Illinois, Urbana, IL Owing to the need for low power consumption, portable and wearable electronics operate at low voltages, typically below 1V, with recent designs in near- and subthreshold operation resul
ISSCC 2017
Session 10
Power Management
A Hybrid Inductor-Based Flying-Capacitor-Assisted Step-Up/Step-Down DC-DC Converter with 96.56% Efficiency
Each mobile device is usually equipped with a Li-ion battery having voltage that varies from a minimum of 2.7V to a maximum of 4.2V. Therefore, as the battery voltage decreases with time, a DC-DC converter is required fo
ISSCC 2017
Session 10
Power Management
A Three-Level Single-Inductor Triple-Output Converter with an Adjustable Flying-Capacitor Technique for Low Output Ripple and Fast Transient Response
devices below 28nm allow supply voltages lower than 1V. For applications with higher input voltage in such devices, stacked MOSFET structures with a three-level technology are commonly employed. The stacked structure can
ISSCC 2017
Session 10
Power Management
A 30MHz Hybrid Buck Converter with 36mV Droop and 125ns 1% Settling Time for a 1.25A/2ns Load Transient
Fast load-transient responses are crucial for DC-DC converters to cope with the demands of modern highly integrated system-on-chip (SoC) designs. Various techniques have been proposed to improve transient responses by en
ISSCC 2017
Session 10
Power Management
A 25MHz 4-Phase SAW Hysteretic DC-DC Converter with 1-Cycle APC Achieving 190ns tsettle to 4A Load Transient and Above 80% Efficiency in 96.7% of the Power Range
Switching power converters with fast load transients are crucial for application processors (APs) to facilitate system-level power adaptability with high current slew rate. While current-mode hysteretic control has been
ISSCC 2017
Session 11
Memory
A 512Gb 3b/Cell Flash Memory on 64-Word-LineLayer BiCS Technology
Toshio Yamamura2, Hiroyuki Mizukoshi1, Shingo Zaitsu1, Minoru Yamashita1, Shunichi Toyama1, Norihiro Kamae1, Juan Lee1, Shuo Chen1, Jiawei Tao1, William Mak1, Xiaohua Zhang1, Ying Yu1, Yuko Utsunomiya2, Yosuke Kato1, Man
ISSCC 2017
Session 11
Memory
A 1Mb Embedded NOR Flash Memory with 39μW Program Power for mm-Scale High-Temperature Sensor Nodes
Jingcheng Wang1, Kaiyuan Yang1, Yen-Po Chen1, Junjie Dong1, Minchang Cho1, Gyouho Kim1, Wei-Keng Chang2, Yun-Sheng Chen2, Yu-Der Chih2, David Blaauw1, Dennis Sylvester1 University of Michigan, Ann Arbor, MI TSMC, Hsinchu
ISSCC 2017
Session 11
Memory
A 10nm 32Kb Low-Voltage Logic-Compatible Anti-Fuse One-Time-Programmable Memory with Anti-Tampering Sensing Scheme
breakdown as a programming scheme is fabricated and characterized. The antifuse OTP bitcell is composed of an NMOS as antifuse element and as a select transistor. Characterization shows that this solution is a viable tec
ISSCC 2017
Session 11
Memory
A 512Gb 3b/cell 64-Stacked WL 3D V-NAND Flash Memory
Doo-Hyun Kim, Daewoon Kang, Sunghoon Lee, Ji-Sang Lee, Wontae Kim, Jiyoon Park, Yang-lo Ahn, Jiyoung Lee, Jong-hoon Lee, Seungbum Kim, Hyun-Jun Yoon, Jaedoeg Yu, Nayoung Choi, Yelim Kwon, Nahyun Kim, Hwajun Jang, Jonghoo
ISSCC 2017
Session 12
Memory
A 7nm 256Mb SRAM in High-K Metal-Gate FinFET Technology with Write-Assist Circuitry for Low-VMIN Applications
Hank Cheng1, Hidehiro Fujiwara1, Jih-Yu Lin1, Kao-Cheng Lin1, John Hung1, Robin Lee1, Hung-Jen Liao1, Jhon-Jhy Liaw2, Quincy Li2, Chih-Yung Lin2, Mu-Chi Chiang2, Shien-Yang Wu2 TSMC Design Technology, Hsinchu, Taiwan TSM
ISSCC 2017
Session 12
Memory
A 7nm FinFET SRAM Macro Using EUV Lithography for Peripheral Repair Analysis
Changnam Park, Minsun Hong, Giyong Yang, Jeongho Do, Jinyoung Lim, Seungyoung Lee, Ingyum Kim, Sanghoon Baek, Jonghoon Jung, Daewon Ha, Hyungsoon Jang, Taejung Lee, Chul-Hong Park, Bongjae Kwon, Hyuntaek Jung, Sungwee Ch
ISSCC 2017
Session 12
Memory
A Low-Power and High-Performance 10nm SRAM Architecture for Mobile Applications
Johnny Yang2, Hau-Tai Hsieh2, Frank Wu2, Jung-Ping Yang2, Atul Katoch3, Arun Achyuthan3, Donald Mikan1, Bryan Sheffield1, Jonathan Chang2 TSMC Design Technology, Austin, TX TSMC Design Technology, Hsinchu, Taiwan 3 TSMC
ISSCC 2017
Session 12
Memory
Gsearch/s 2Mb/mm2 TCAM Using Two-PhasePrecharge ML Sensing and Power-Grid PreConditioning to Reduce Ldi/dt Power-Supply Noise by 50%
Van Butler1,2, Raymond Kim3, Ramon Rodriguez1, Tom Maffitt4, Joseph J. Oler1, John Goss1, Christopher Parkinson5,6, Michael A. Ziegerhofer1, Steven Burns1 Globalfoundries, Essex Junction, VT Green Mountain Semiconductor,
ISSCC 2017
Session 13
RF & Wireless
A Fully Integrated Multimode Front-End Module for GSM/EDGE/TD-SCDMA/TD-LTE Applications Using a Class-F CMOS Power Amplifier
Chien-Wei Tseng1, Lai-Ching Lin1, Chris Beale2, Bosen Tseng1, Bernard Tenbroek2, Chinq-Shiun Chiu1, Guang-Kaai Dehng1, George Chien3 MediaTek, Hsinchu, Taiwan MediaTek, Kent, United Kingdom 3 MediaTek, San Jose, CA 1 2 T
ISSCC 2017
Session 13
RF & Wireless
A >1W 2.2GHz Switched-Capacitor Digital Power Amplifier with Wideband Mixed-Domain Multi-Tap FIR Filtering of OOB Noise Floor
Digital power amplifiers and transmitters have drawn significant interest in the recent past due to their reconfigurability, compatibility with CMOS technology scaling and DSP, and potential for automated design synthesi
ISSCC 2017
Session 13
RF & Wireless
A Digital Multimode Polar Transmitter Supporting 40MHz LTE Carrier Aggregation in 28nm CMOS
Jonas Fritzin1, Hans Geltinger2, Marcus Groinig3, Daniel Gruber3, Simon Gruenberger3, Thomas Hartig3, Vahur Kampus3, Boris Kapfelsberger1, Franz Kuttner3, Stephan Leuschner1, Thomas Maletz1, Andreas Menkhoff1, Jose Morei
ISSCC 2017
Session 13
RF & Wireless
A SAW-Less Reconfigurable Multimode Transmitter with a Voltage-Mode Harmonic-Reject Mixer in 14nm FinFET CMOS
Multimode cellular RFICs need high dynamic range in order to simultaneously satisfy the high linearity requirements of LTE and the low-noise performance of 2G. Traditionally, SAW filters are employed to relax the noise-l
ISSCC 2017
Session 13
RF & Wireless
All-Digital RF Transmitter in 28nm CMOS with Programmable RX-Band Noise Shaping
Paul Stynen2, Kaoutar Bertrand2, Teuvo Korhonen2, Hans Samsom2, Patrick Vandenameele2, Jussi Ryynänen1 Aalto University, Espoo, Finland Huawei Technologies, Leuven, Belgium 1 The TX prototype was fabricated in 28nm CMOS
ISSCC 2017
Session 13
RF & Wireless
A 0.35-to-2.6GHz Multilevel Outphasing Transmitter with a Digital Interpolating Phase Modulator Enabling up to 400MHz Instantaneous Bandwidth
Tero Nieminen1, Mikko Englund1, Kari Stadius1, Lauri Anttila2, Jorma Pallonen3, Mikko Valkama2, Jussi Ryynänen1 Aalto University, Espoo, Finland Tampere University of Technology, Tampere, Finland 3 Nokia, Espoo, Finland
ISSCC 2017
Session 13
RF & Wireless
A 2.4GHz WLAN Digital Polar Transmitter with Synthesized Digital-to-Time Converter in 14nm Trigate/FinFET Technology for IoT and Wearable Applications
Muhammad Faisal1,b, William Yee Li1, Hyung Seok Kim1, Khoa Minh Nguyen1, Yulin Tan1,c, Brent Carlton1, Vaibhav Vaidya1, Yanjie Wang1, Thomas Tetzlaff1, Satoshi Suzuki1, Amr Fahim1,d, Parmoon Seddighrad1, Jianyong Xie2, Z
ISSCC 2017
Session 13
RF & Wireless
A 0.23mm2 Digital Power Amplifier with Hybrid Time/Amplitude Control Achieving 22.5dBm at 28% PAE for 802.11g
Ashkan Olyaei2, Ovidiu Carnu2, Philip Godoy2, Alden Wong2, Xingliang Zhao2, Jiexi Liu2, Arnab Mitra2, Randy Tsang2, Li Lin2 Marvell, Etoy, Switzerland 2 Marvell, Santa Clara, CA 1 Integration of digital RF transmitters a
ISSCC 2017
Session 13
RF & Wireless
A 24dBm 2-to-4.3GHz Wideband Digital Power Amplifier with Built-In AM-PM Distortion SelfCompensation
spectrum-efficient modulation schemes such as 64QAM and 256QAM and high data-rates. This poses stringent requirements on RF Power Amplifiers (PAs) for their carrier bandwidth, linearity, modulation rate, and efficiency.
ISSCC 2017
Session 13
RF & Wireless
A 1.1V 28.6dBm Fully Integrated Digital Power Amplifier for Mobile and Wireless Applications in 28nm CMOS Technology with 35% PAE
wireless applications emerge, calling for increasingly higher integration and smaller footprint, while ensuring high reliability and operation at limited supply voltages. In this context, the integration of the power amp
ISSCC 2017
Session 14
AI / ML
A 2.9TOPS/W Deep Convolutional Neural Network SoC in FD-SOI 28nm for Intelligent Embedded Systems
Elio Guidetti1, Fabio De Ambroggi4, Tommaso Majo1, Paolo Zambotti4, Manuj Ayodhyawasi2, Harvinder Singh2, Nalin Aggarwal2 STMicroelectronics, Cornaredo, Italy STMicroelectronics, Greater Noida, India 3 STMicroelectronics
ISSCC 2017
Session 14
AI / ML
DNPU: An 8.1TOPS/W Reconfigurable CNN-RNN Processor for General-Purpose Deep Neural Networks
Recently, deep learning with convolutional neural networks (CNNs) and recurrent neural networks (RNNs) has become universal in all-around applications. CNNs are used to support vision recognition and processing, and RNNs
ISSCC 2017
Session 14
Digital Processors
A 28nm SoC with a 1.2GHz 568nJ/Prediction Sparse Deep-Neural-Network Engine with >0.1 Timing Error Rate Tolerance for IoT Applications
(IoT) devices with the capability to interpret the complex, noisy real-world data arising from sensorrich systems. Achieving sufficient energy efficiency to execute ML workloads on an edge-device necessitates specialized
ISSCC 2017
Session 14
Digital Processors
A Scalable Speech Recognizer with Deep-NeuralNetwork Acoustic Models and Voice-Activated Power Gating
Analog Devices, Cambridge, MA 1 Previous work such as [4] provided micropower VADs that can be used in quiet environments or in applications that tolerate false alarms. In our application, false alarms will unnecessarily
ISSCC 2017
Session 14
AI / ML
ENVISION: A 0.26-to-10TOPS/W Subword-Parallel Dynamic-Voltage-Accuracy-Frequency-Scalable Convolutional Neural Network Processor in 28nm FDSOI
ConvNets, or Convolutional Neural Networks (CNN), are state-of-the-art classification algorithms, achieving near-human performance in visual recognition
ISSCC 2017
Session 14
Digital Processors
A 0.62mW Ultra-Low-Power Convolutional-NeuralNetwork Face-Recognition Processor and a CIS Integrated with Always-On Haar-Like Face Detector
for the next-generation UI/UX of wearable devices. A FR system, shown in Fig. 14.6.1, was developed as a life-cycle analyzer or a personal black box, constantly recording the people we meet, along with time and place inf
ISSCC 2017
Session 14
Digital Processors
A 288μW Programmable Deep-Learning Processor with 270KB On-Chip Weight Storage Using Non-Uniform Memory Hierarchy for Mobile Intelligence
Qing Dong1, Yen-Po Chen1, Laura Fick1, Xun Sun1, Ron Dreslinski1, Trevor Mudge1, Hun Seok Kim1, David Blaauw1, Dennis Sylvester1 University of Michigan, Ann Arbor, MI CubeWorks, Ann Arbor, MI 1 2 Deep learning has proven
ISSCC 2017
Session 14
Digital Processors
A 135mW Fully Integrated Data Processor for Next-Generation Sequencing
National Chiao Tung University, Hsinchu, Taiwan 1 2 DNA sequencing is the process of determining the precise order of nucleotides (A, C, G, T) within a DNA molecule and is now indispensable for genetics and medical resea
ISSCC 2017
Session 15
Other
Large-Scale Acquisition of Large-Area Sensors Using an Array of Frequency-Hopping ZnO Thin-Film-Transistor Oscillators
James C. Sturm, Naveen Verma Princeton University, Princeton, NJ Hybrid systems combine Large-Area Electronics (LAE) and silicon CMOS ICs for sensing and computation, respectively. Such systems are limited in number of s
ISSCC 2017
Session 15
Other
A Flexible ISO14443-A Compliant 7.5mW 128b Metal-Oxide NFC Barcode Tag with Direct Clock Division Circuit from 13.56MHz Carrier
Marc Ameys1, Myriam Willegems1, Steve Smout1, Soeren Steudel1, Wim Dehaene1,3, Jan Genoe1,3 imec, Heverlee, Belgium AU Optronics, Hsinchu, Taiwan 3 KU Leuven, Leuven, Belgium 1 2 Flexible low-cost RFID/NFC tags have grea
ISSCC 2017
Session 15
Other
An a-IGZO Asynchronous Delta-Sigma Modulator on Foil Achieving up to 43dB SNR and 40dB SNDR in 300Hz Bandwidth 3.4kHz and increases robustness against batch to batch variations. At the comparator output a source follower drives the current DAC. This is composed of a current source and four switches, implemented as double gate TFTs with gate and TG connected together.
Gerwin H. Gelinck2, Arthur H. M. Van Roermund1, Eugenio Cantatore1 Figure 15.3.3 shows the measured ADSM output spectrum for a 100Hz IIN with -7dBFS amplitude: the fundamental, the limit cycle fundamental at 2kHz and its
ISSCC 2017
Session 15
Other
A 1024-Element Scalable Optical Phased Array in 0.18µm SOI CMOS
Self-driving cars, drones, and other autonomous systems rely on a number of sensors such as cameras, radars, and ultrasonic detectors to observe their surrounding environments. Light detection and ranging (lidar), where
ISSCC 2017
Session 15
Other
Cryo-CMOS Circuits and Systems for Scalable Quantum Computing
Andrei Vladimirescu4,5, Mina Shahmohammadi1, Robert Bogdan Staszewski1, Harald A.R. Homulle1, Bishnu Patra1, Jeroen P.G. van Dijk1, Rosario M. Incandela1, Lin Song1,6, Bahador Valizadehpasha1 Delft University of Technolo
ISSCC 2017
Session 15
Other
A 30-to-80MHz Simultaneous Dual-Mode Heterodyne Oscillator Targeting NEMS Array Gravimetric Sensing Applications with a 300zg Mass Resolution
scale physical variations has led to the breakthrough development of NEMS-based mass spectrometry systems capable of measuring a single molecule [1]. Parallel sensing using thousands of devices will help to circumvent th
ISSCC 2017
Session 15
Other
Heterogeneous Integrated CMOS-Graphene Sensor Array for Dopamine Detection
for advancing our knowledge of pathological disorders such as drug addiction, Parkinson’s disease, and schizophrenia. Currently, fast-scan cyclic voltammetry (FSCV) with carbon microfiber (CMF) electrodes is the method o
ISSCC 2017
Session 15
Other
A Permanent Digital Archive System Based on 4F2 X-Point Multi-Layer Metal Nano-Dot Structure
Data is saved by the presence of a metal nano-dot at a x-point of interconnects. This passive storage node works as a permanent memory cell with >1,000-years endurance. No transistor is used in the cell, enabling multi-l
ISSCC 2017
Session 15
Other
An Integrated Optical Physically Unclonable Function Using Process-Sensitive Sub-Wavelength Photonic Crystals in 65nm CMOS power meter to characterize the incident power, while the other half of the laser light shines uniformly on the chip under test. This setup is used to characterize the spectral responsivity of the photonic crystal, but is not required to generate responses for the PUF signature. The photonic structure itself serves as a linear polarizer that rejects incoming light in other polarization.
Physical unclonable function (PUF) is regarded as an emerging solution for reliable cryptography. Rather than storing secret keys in memories, the information of a PUF is extracted through amplification of the physically
ISSCC 2017
Session 16
Data Converters
A 13b 4GS/s Digitally Assisted Dynamic 3-Stage Asynchronous Pipelined-SAR ADC
Conrado Mesadri1, Ali Boumaalif3, John Mcgrath3, Umanath Kamath1, Ronnie De Le Torre1, Alvin Manlapat1, Daire Breathnach3, Christophe Erdmann1, Brendan Farley1 Xilinx, Dublin, Ireland Xilinx, San Jose, CA 3 Xilinx, Cork,
ISSCC 2017
Session 16
Data Converters
A 9GS/s 1GHz-BW Oversampled Continuous-Time Pipeline ADC Achieving -161dBFS/Hz NSD
front-end by a switchedcapacitor circuit and all internal signals are processed in discrete-time (DT) even though the front-end sampler introduces artifacts such as aliasing, noise folding, and high-peak ADC driving curr
ISSCC 2017
Session 16
Data Converters
A 330mW 14b 6.8GS/s Dual-Mode RF DAC in 16nm FinFET Achieving -70.8dBc ACPR in a 20MHz Channel at 5.2GHz
Bob Verbruggen, John Mcgrath, Diarmuid Collins, Marites De La Torre, Pierrick Gay, Patrick Lynch, Peng Lim, Anthony Collins, Brendan Farley Xilinx, Dublin, Ireland Direct-RF synthesis has gained increasing attention in r
ISSCC 2017
Session 16
Data Converters
A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with Background Offset Calibration
Wireless communication systems and Ethernet networks call for moderateresolution GS/s energy-efficient ADCs. While previous work [1] shows that the multi-bit per cycle SAR ADC can achieve low power due to various hardwar
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