⚡ 本页包含 AI 生成的分析内容，仅供参考
本文提出一种0.7V供电、12位分辨率、160MS/s采样率的流水线-逐次逼近型模数转换器（Pipelined-SAR ADC），采用数字放大器技术替代传统MDAC中的高增益运算放大器，在28nm CMOS工艺下实现了12.8fJ/转换步进的能效，解决了深亚微米CMOS中高增益运算放大器设计困难的问题。
g. 802.11ac Wave 2 and 802.11ax draft, aim to boost user throughput to cope with growing data traffic. High-speed (fs>100MS/s) and highresolution (ENOB>9.5b) ADCs are essential for leading-edge wireless SoCs, given the bandwidth and PAPR specifications. Also, low power dissipation (FoM<20fJ/conv) is crucial for mobile applications. A number of pipelined-SAR ADCs have been presented which satisfy these design targets [1-3]. However, in deep submicron CMOS, design of a high DC-gain opamp for the MDAC is a serious obstacle due to reduced intrinsic transistor gain and sub-1V supply voltage. Hence, all designs utilize digital calibration to counter gain error and tolerate the use of a low-gain amplifier. Calibration times of at least several tens of ms are required, resulting in lengthy start-up times and reduced SoC power
Kentaro Yoshioka, Tomohiko Sugimoto, Naoya Waki, Sinnyoung Kim,
Daisuke Kurose, Hirotomo Ishii, Masanori Furuta, Akihide Sai, Tetsuro Itakura Toshiba, Kawasaki, Japan Wireless standards, e