A 5Gb/s/pin 8Gb LPDDR4X SDRAM with PowerIsolated LVSTL and Split-Die Architecture with 2-Die ZQ Calibration Scheme

📋 论文概要

本文提出了一款5Gb/s/pin的8Gb LPDDR4X SDRAM，采用PowerIsolated LVSTL和Split-Die架构，并引入2-Die ZQ校准方案，以满足低功耗移动应用如可穿戴设备和智能手机的需求。

💡 主要创新点

• 提出PowerIsolated LVSTL（电源隔离的低压摆幅终端逻辑），降低功耗并提高信号完整性。
• 采用Split-Die架构，将芯片分割为两个独立区域，优化布局和性能。
• 引入2-Die ZQ校准方案，实现两个芯片之间的阻抗匹配，提高数据传输可靠性。

🏷 关键词

📄 原文摘要

Kihan Kim, Young Choi, Ho-Jun Chang, Jonghyuk Kim, Jong-Min Bang, Seungjun Shin, Hanna Park, Sujin Park, Young-Ryeol Choi, Hoon Lee, Kyong-Ho Jeon, Jae-Young Lee, Hyo-Joo Ahn, Kyoung-Ho Kim, Jung-Sik Kim, Soobong Chang, Hyong-Ryol Hwang, Duyeul Kim, Yoon-Hwan Yoon, Seok-Hun Hyun, Joon-Young Park, Yoon-Gyu Song, Youn-Sik Park, Hyuck-Joon Kwon, Seung-Jun Bae, Tae-Young Oh, In-Dal Song, Yong-Cheol Bae, Jung-Hwan Choi, Kwang-Il Park, Seong-Jin Jang, Gyo-Young Jin Samsung Electronics, Hwasung, Korea With growing demand for low-power mobile applications, such as wearable devices, smart phones and tablet PCs, low-power mobile DRAM has been identified as a mandatory requirement for low-power system designs. The recently developed LPDDR4 [1] is still a power efficient solution because of its architectural approaches and low-voltage-swing terminated logic (LVSTL). However, demand for enhanced power-efficiency beyond LPDDR4 is still increasing for mobile

👥 作者与机构

Chang-Kyo Lee, Yoon-Joo Eom, Jin-Hee Park, Junha Lee, Hye-Ran Kim,