A 2.5ps 0.8-to-3.2GHz Bang-Bang Phase- and Frequency-Detector-Based All-Digital PLL with Noise Self-Adjustment

📋 论文概要

提出了一种基于Bang-Bang相位和频率检测器的全数字锁相环(PLL)，通过噪声自调整技术来应对工艺、电压和温度(PVT)变化导致的性能退化。该PLL实现了0.8至3.2GHz的宽频率范围，并获得了2.5ps的RMS抖动。

💡 主要创新点

• 采用Bang-Bang相位和频率检测器实现全数字PLL，避免了模拟电路对PVT变化的敏感性
• 提出噪声自调整机制，动态补偿DCO增益和噪声变化，提高环境适应性

🏷 关键词

📄 原文摘要

their small size and technology portability. Variability tolerance is a key design challenge when designing such PLLs in an advanced CMOS technology. Environmental variations, such as mismatch, process, supply voltage, and temperature (PVT) perturb device characteristics and result in performance changes, such as DCO gain and noise. Another consideration is the wide range of operating modes in which modern digital circuits (e.g., processors) operate. For instance, a clock generator for a processor may produce a range of frequencies from tens of MHz to several GHz depending on required processor performance. In low-frequency mode, the power consumption is more pronounced than the noise. Therefore, we seek to design a

👥 作者与机构

Taekwang Jang1, Seokhyeon Jeong1, Dongsuk Jeon2, Kyojin David Choo1,

Dennis Sylvester1, David Blaauw1 University of Michigan, Ann Arbor, MI Seoul National University, Seoul, Korea 1 2 Digital PLLs are popular for on-chip clock generation due to