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本文介绍了POWER9处理器家族，针对认知计算和云基础设施需求，通过四种芯片配置提供灵活、可扩展的解决方案，并实现了25Gb/s加速器链路和16Gb/s PCIe Gen4接口。该设计解决了高带宽IO和多样化内存、核心线程及加速器选项的挑战。
Rahul Rao3, Jose Paredes2, Michael Floyd2, Michael Sperling4, Ryan Kruse2, Vinod Ramadurai2, Ryan Nett2, Saiful Islam2, Juergen Pille5, Donald Plass4 IBM, Yorktown Heights, NY IBM, Austin, TX 3 IBM, Bangalore, India 4 IBM, Poughkeepsie, NY 5 IBM, Boblingen, Germany 1 2 Cognitive computing and cloud infrastructure require flexible, connectable, and scalable processors with extreme IO bandwidth. With 4 distinct chip configurations, the POWER9 family of chips delivers multiple options for memory ports, core thread counts, and accelerator options to address this need. The 24core scale-out processor is implemented in 14nm SOI FinFET technology [1] and contains 8.0B transistors. The 695mm2 chip uses 17 levels of copper interconnect: 3-64nm, 2-80nm, 4-128nm, 2-256nm, 4-360nm pitch wiring for signals and 22400nm pitch wiring levels for power and global clock distribution. Digital logic uses three thin-oxide transistor Vts to balance power and performance
Christopher Gonzalez1, Eric Fluhr2, Daniel Dreps2, David Hogenmiller2,