A 10nm 32Kb Low-Voltage Logic-Compatible Anti-Fuse One-Time-Programmable Memory with Anti-Tampering Sensing Scheme

📋 论文概要

该论文提出了一种在10nm工艺下实现的32Kb低压逻辑兼容反熔丝一次性可编程存储器，采用NMOS作为反熔丝元件和选择晶体管，并利用防篡改传感方案来提高安全性。该设计解决了先进工艺中逻辑兼容OTP的需求，适用于SRAM修复和安全信息存储。

💡 主要创新点

• 采用10nm逻辑兼容工艺实现低压反熔丝OTP，使用NMOS同时作为反熔丝元件和选择晶体管，简化了单元结构。
• 提出防篡改传感方案，增强存储器的安全性，防止未授权读取或篡改。
• 实现了32Kb容量的低电压操作，适应先进工艺下的低功耗需求。

🏷 关键词

📄 原文摘要

breakdown as a programming scheme is fabricated and characterized. The antifuse OTP bitcell is composed of an NMOS as antifuse element and as a select transistor. Characterization shows that this solution is a viable technology option for modern OTP and electrical fuse applications. A logic process compatible OTP is a very important segment in an advanced technology’s memory portfolio: it can be used to store, for example, SRAM repair or security related information. Several solutions were introduced for logic process compatible OTP applications. An electrical fuse [1], composed of a transistor and a resistive element, is one of the most popular OTP candidates. However, because an electrical fuse needs a high current to accumulate during program, the cell size of the electrical fuse must be several times larger than that

👥 作者与机构

Shau-Yu Chou, Yu-Shiang Chen, Jun-Hao Chang, Yu-Der Chih, Tsung-Yung Jonathan Chang

TSMC Design Technology, Hsinchu, Taiwan A two-transistor antifuse OTP memory macro using permanent MOS-gate-oxide