A 14nm Fractional-N Digital PLL with 0.14psrms Jitter and -78dBc Fractional Spur for Cellular RFICs

📋 论文概要

该论文提出了一种用于蜂窝射频集成电路的14nm分数分频数字锁相环，实现了0.14psrms的抖动和-78dBc的分数杂散，解决了载波聚合和256QAM等高级LTE技术对低抖动、低杂散时钟的需求。

💡 主要创新点

• 采用数字锁相环架构，在14nm FinFET工艺下实现了极低的抖动和分数杂散性能。
• 通过优化的数字环路滤波器和分数分频器设计，有效抑制了分数杂散，满足蜂窝射频的严格要求。

🏷 关键词

📄 原文摘要

Haoyang Li1, Kunal Godbole1, Yongrong Zuo1, Sangsoo Ko2, Nam-Seog Kim2, Sangwook Han2, Ikkyun Jo2, Joonhee Lee2, Juyoung Han2, Daehyeon Kwon2, Chulho Kim2, Shinwoong Kim2, Sang Won Son1, Thomas Byunghak Cho2 Samsung Semiconductor, San Jose, CA Samsung Electronics, Hwasung, Korea 1 2 To meet ever-growing demands for higher mobile data-rates, LTE standards continue to evolve. While carrier aggregation (CA) improves data-rates, it requires wider aggregated signal bandwidth that limits the number of users that can be serviced. Techniques like 256QAM and 4×4 MIMO are attractive because improvements do not need wider signal bandwidth. To support 256QAM and 4×4 MIMO for the 5GHz band, we need IPN better than -48dBc or 155fsec rms. A digital fractional-N PLL that achieves 137fsec rms jitter integrating from 10kHz to 10MHz (or 142fsec 1kHz to 10 MHz) with a -78.6dBc near integer-N fractional spur is presented. We have introduced a TDC chopping technique, fine-conversion

👥 作者与机构

Chih-Wei Yao1, Wing Fai Loke1, Ronghua Ni1, Yongping Han1,