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本文提出了一种基于反相器的低压差稳压器（LDO），采用65nm CMOS工艺，在最低0.2V电源电压下实现了轨到轨调节和超过-20dB的电源抑制比（PSR），解决了超低压操作下LDO的噪声抑制和调节难题，适用于动态电压频率调整（DVFS）系统中的点负载供电。
Ultra-low-voltage operation is highly demanded in a system that adopts the DVFS scheme, e.g., a portable device that sustains days-long standby with a tiny battery. Such a system usually embeds modules that have specific minimum supply voltages. Point-of-load low-dropout regulators (LDOs) are used to power these modules as per the required applications, from a global supply rail Vdd. The global Vdd is noisy and can be varied within a wide range, which adds to the difficulty of designing LDOs in such applications. Over the past decade, digital LDOs (DLDOs) have been developed to work under a greatly lowered Vdd [1-4]. DLDOs utilize all-digital logic or time-to-digital conversion to replace the all-analog controller, and have no headroom in fully switching on/off the pass transistor. Current DLDOs are very competitive in providing fast-response regulation; however, when in idle mode, they are
Fan Yang, Philip K. T. Mok
Hong Kong University of Science and Technology, Hong Kong, China