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ISSCC 2017Session 14 · DEEP-LEARNING PROCESSORSAI / ML65nm CMOS

DNPU: An 8.1TOPS/W Reconfigurable CNN-RNN Processor for General-Purpose Deep Neural Networks

⚡ 本页包含 AI 生成的分析内容,仅供参考

📋 论文概要

该论文提出了一款名为DNPU的可重构CNN-RNN处理器,通过统一架构同时高效支持卷积神经网络和循环神经网络,解决了不同网络计算需求差异大的问题,实现了8.1TOPS/W的高能效。

💡 主要创新点

核心指标
8.1TOPS/W
工艺节点
65nm CMOS
重要性
发表年份
ISSCC 2017

🏷 关键词

可重构处理器卷积神经网络循环神经网络高能效深度学习

📄 原文摘要

Recently, deep learning with convolutional neural networks (CNNs) and recurrent neural networks (RNNs) has become universal in all-around applications. CNNs are used to support vision recognition and processing, and RNNs are able to recognize time varying entities and to support generative models. Also, combining both CNNs and RNNs can recognize time varying visual entities, such as action and gesture, and to support image captioning [1]. However, the computational requirements in CNNs are quite different from those of RNNs. Fig. 14.2.1 shows a computation and weight-size analysis of convolution layers (CLs), fullyconnected layers (FCLs) and RNN-LSTM layers (RLs). While CLs require a massive amount of computation with a relatively small number of filter weights, FCLs and RLs require a relatively small amount of computation with a huge number of filter weights. Therefore, when FCLs and RLs are accelerated with SoCs

👥 作者与机构

Dongjoo Shin, Jinmook Lee, Jinsu Lee, Hoi-Jun Yoo

KAIST, Daejeon, Korea

分类:AI / ML · 年份:ISSCC 2017