⚡ 本页包含 AI 生成的分析内容，仅供参考
该论文提出了一款12位10GS/s的交织流水线ADC，采用28nm CMOS工艺，实现了7.4GHz的输入模拟带宽，适用于软件定义无线电和宽带仪器等需要高动态范围的应用。
Jose Silva1, Janet Brunsilius2, Daniel Rey-Losada2, Frank Murden3, Carroll Speir3, Jeff Bray2, Eric Otte1, Nevena Rakuljic2, Phil Brown3, Todd Weigandt2, Qicheng Yu1, Donald Paterson1, Corey Petersen2, Jeffrey Gealow1 Analog Devices, Wilmington, MA Analog Devices, San Diego, CA 3 Analog Devices, Greensboro, NC 1 2 Software defined radios and wideband instrumentation demand the ability to digitize wide BW RF signals with moderately high dynamic range. A 12b 10GS/s ADC with an input analog bandwidth of 7.4GHz is developed for such applications in 28nm CMOS. The ADC achieves an SNR of 56dB, SNDR of 55dB and SFDR of 64dB with a 4GHz input at 10GS/s, and realizes an NSD of -157dBFS/Hz (i.e. DR = 60dB) while dissipating 2.9W. While interleaving (IL) enables high sample rates [1-5], the key challenges with interleaving are: 1) the load presented to the ADC input by the interleaved array, which severely limits BW and introduces distortion; 2) sensitivity to mismatches
Siddharth Devarajan1, Larry Singer1, Dan Kelly1, Steve Kosic2, Tao Pan1,