Digital Low-Dropout Regulator with Anti PVT-Variation Technique for Dynamic Voltage Scaling and Adaptive Voltage Scaling Multicore Processor

📋 论文概要

本文提出了一种具有抗PVT变化技术的数字低压差稳压器（DLDO），用于动态电压缩放（DVS）和自适应电压缩放（AVS）应用。该技术旨在提高稳压器在不同工艺、电压和温度条件下的稳定性和性能，从而实现快速、低成本且节能的片上电源管理。

💡 主要创新点

• 提出了一种抗PVT变化的技术，使数字LDO在工艺、电压和温度变化下仍能保持稳定和高效。
• 针对DVS和AVS应用优化了数字LDO的带宽和响应速度，支持快速电压调节。

🏷 关键词

📄 原文摘要

processors have been widely used in battery-operated portable systems, desktop, and server applications, where dynamic voltage scaling (DVS) and adaptive voltage scaling (AVS) techniques are commonly employed to lower power consumption and improve thermal performance of the cores. In Fig. 20.2.1, high-bandwidth digital low-dropout (DLDO) regulators are used to achieve fast, cost-effective, and energy-efficient functions for on-chip power domains. Nowadays, processor vendors provide software for DVS, allowing the processor to scale the VOUT to the desired operating-performance point (OPP). However, the DLDO produces an undesirable output voltage ripple ΔVOUT due to process, voltage, and temperature (PVT) variations. More specifically, the DLDO has a

👥 作者与机构

Wen-Jie Tsou1, Wen-Hau Yang1, Jian-He Lin1, Hsin Chen1,

Ke-Horng Chen1, Chin-Long Wey1, Ying-Hsi Lin2, Shian-Ru Lin2, Tsung-Yen Tsai2 National Chiao Tung University, Hsinchu, Taiwan Realtek Semiconductor, Hsinchu, Taiwan 1 2 Multicore