A 4.8Gb/s/pin 2Gb LPDDR4 SDRAM with Sub-100μA Self-Refresh Current for IoT Applications

📋 论文概要

该论文提出了一款面向物联网应用的2Gb LPDDR4 SDRAM，实现了4.8Gb/s/pin的数据速率和低于100μA的自刷新电流。通过创新的低功耗电路设计，在保持高速性能的同时显著降低了待机功耗，满足了物联网设备对低功耗和高响应速度的需求。

💡 主要创新点

• 实现了低于100μA的自刷新电流，大幅降低待机功耗，适合电池供电的物联网设备。
• 在LPDDR4接口上达到4.8Gb/s/pin的高速数据传输速率，兼顾低功耗与高性能。
• 可能采用了新型的电路架构或工艺优化，在2Gb容量下实现极低功耗的自我刷新操作。

🏷 关键词

📄 原文摘要

Mun Seon Jang, Yongsuk Joo, Seung-Hun Lee, Woo Young Lee, Eunryeong Lee, Donghee Han, Jaeyeol Kang, Jung Ho Lim, Jae-Beom Park, Kyung-Tae Kim, Sunki Cho, Sung Woo Han, Jee Yeon Keh, Jun Hyun Chun, Jonghoon Oh, Seok Hee Lee SK hynix, Icheon, Korea The internet of things (IoT) requires that more data are collected and processed by devices with faster response, but lower power consumption. In order to achieve these unprecedented requirements, a high-speed DRAM with low-power dissipation at standby and during low-frequency operation in a small footprint is necessary. In addition, a higher degree of reliability is expected for some applications: such as transportation and healthcare. One promising solution, onchip error correction coding (ECC), has gained traction among memory companies [1] and is now required by the LPDDR4 standard for the first time [2]. In this paper, a 2Gb LPDDR4 that dissipates 75% less refresh current than a

👥 作者与机构

Nohhyup Kwak, Saeng-Hwan Kim, Kyong Ha Lee, Chang-Ki Baek,