⚡ 本页包含 AI 生成的分析内容，仅供参考
本文针对22nm工艺的z13微处理器，采用系统级方法进行电源噪声抑制，包括设计抑制电路并与电源分配网络建模协同。解决了高性能处理器中电源噪声导致的性能下降和可靠性问题。
Richard Rizzolo3, Tobias Webel4, Thomas Strach4, Otto Torreiter4, Preetham Lobo5, Alper Buyuktosunoglu1, Ramon Bertran1, Michael Floyd6, Malcolm Ware6, Gerard Salem7, Sean Carey8, Phillip Restle1 IBM Research, Yorktown Heights, NY 2 Drexel University, Philadelphia, PA 3 IBM, Poughkeepsie, NY 4 IBM STG, Boeblingen, Germany 5 IBM STG, Bangalore, India 6 IBM STG, Austin, TX 7 IBM STG, Burlington, NY 8 IBM STG, Poughkeepsie, NY 1 Successful power supply noise mitigation requires a system-level approach that includes design and modeling of the mitigation circuits with the power delivery network (PDN) on the chip, the chip module, the backplane, and the voltage regulator module (VRM). Traditionally, periodic square-wave activity patterns with all cores in sync, which yield low-frequency (LF) or mid-frequency (MF) impedance peaks associated with the backplane and chip/module, respectively, are considered to give rise to the worst case power supply noise. However, voltage
Pierce I-Jen Chuang1, Christos Vezyrtzis1, Divya Pathak2,