A 0.4-to-1V 1MHz-to-2GHz Switched-Capacitor Adiabatic Clock Driver Achieving 55.6% Clock Power Reduction

📋 论文概要

该论文提出了一种基于开关电容的绝热时钟驱动器，能够在0.4V至1V的宽电压范围和1MHz至2GHz的宽频率范围内工作，实现了55.6%的时钟功耗降低，解决了传统谐振时钟方案在低于2GHz频率下难以集成电感的问题。

💡 主要创新点

• 提出了一种开关电容绝热时钟驱动架构，无需电感即可实现谐振式时钟功耗降低，适用于宽电压和频率范围。
• 通过绝热开关技术，动态回收时钟网络电荷，大幅降低功耗，实测显示时钟功耗降低55.6%。
• 支持从亚阈值到近阈值电压的DVFS操作，适应现代SoC低功耗需求。

🏷 关键词

📄 原文摘要

Clock distribution in modern SoCs consumes a significant fraction of total chip power. To reduce clock distribution power, resonant clocking schemes, where an inductive reactance is used to cancel the capacitive reactance of global clock networks at a given resonance frequency, fo, have been proposed. Conventionally, such schemes are only suitable at high multi-GHz frequencies in order to be able to place the employed inductors on chip [1, 2]. Since many modern energyefficient SoC designs optimize for clock frequencies <2GHz, with DVFS techniques bringing the core clock frequencies and the supply voltages VDD to the MHz and near-threshold regimes, respectively, there is a need to develop low-power clock distribution schemes that can work across increasingly wider operating ranges. Recent work in quasi-continuous resonant clocking has proposed intermittent cancelation of global clock-tree capacitance during edge transitions, however,

👥 作者与机构

Loai G. Salem, Patrick P. Mercier

University of California, San Diego, CA