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该论文提出一种三电平单电感三输出（SITO）转换器，采用可调飞电容技术，旨在降低输出纹波。它针对28nm以下工艺中高输入电压应用，通过堆叠MOSFET结构实现低纹波和三个独立输出。
devices below 28nm allow supply voltages lower than 1V. For applications with higher input voltage in such devices, stacked MOSFET structures with a three-level technology are commonly employed. The stacked structure can also reduce the output voltage ripple substantially. Figure 10.5.1 shows a threelevel single-inductor triple-output (SITO) converter and also compares the transient response with the SITO converter without the three-level technique. The three-level topology applies three different voltages, Vin, 1/2Vin, and VSS, to the node VX. The operation mode is determined by the duty cycle, i.e., the node Vx swings between 1/2Vin and VSS when duty cycle (D < 0.5), and between 1/2Vin and Vin, otherwise (D>0.5). In state-of-the-art [1-3], the key issue of the three-level
Li-Cheng Chu1, Wen-Hau Yang1, Xiao-Qing Zhang1, Yan-Jiun Lai1,
Ke-Horng Chen1, Chin-Long Wey1, Ying-Hsi Lin2, Shian-Ru Lin2, Tsung-Yen Tsai2 National Chiao Tung University, Hsinchu, Taiwan Realtek Semiconductor, Hsinchu, Taiwan 1 2 Advanced CMOS