A 50-to-66GHz 65nm CMOS All-Digital Fractional-N PLL with 220fsrms Jitter

📋 论文概要

该论文提出了一款工作在50-66GHz的全数字分数N锁相环，采用65nm CMOS工艺，解决了毫米波合成器中数字PLL因DCO调谐分辨率有限和TDC相位数字化难题而难以应用的问题。通过新型架构设计，实现了220fs rms的低抖动性能。

💡 主要创新点

• 采用全数字架构实现毫米波频段分数N合成，避免了传统模拟PLL的复杂性和整数N限制。
• 优化DCO-TDC接口，降低了功率消耗和面积开销，同时抑制了带内相位噪声。

🏷 关键词

📄 原文摘要

Digital-PLL frequency synthesizers for wireless applications have become popular in the sub-10GHz range. However, mm-wave synthesizers still rely on analog PLLs, predominantly of the integer-N type [1]. This is due to limited DCO tuning resolution and challenges in phase digitization including limited resolution, linearity, and input frequency of the TDC. The 60GHz ADPLL in [2] uses a 32× CML/injection-locked-frequency-divider chain in the DCO-TDC interface, which results in high power consumption (>0.5 of total power), large area, and high inband phase noise. This paper presents a 60GHz phase-domain ADPLL with a 16GHz tuning range, digital phase extraction at fDCO/4, and several on-chip calibration techniques that enable low in-band phase noise and spurs. The ADPLL (Fig. 19.3.1) comprises a 50-to-66GHz DCO followed by an inductorless 4× divider to provide a reasonable input frequency for the phase

👥 作者与机构

Ahmed Hussein, Sriharsha Vasadi, Mazen Soliman, Jeyanandh Paramesh

Carnegie Mellon University, Pittsburgh, PA