A Low-Power and High-Performance 10nm SRAM Architecture for Mobile Applications

📋 论文概要

本文提出了一种用于移动应用的10nm SRAM架构，通过动态时钟发生器直接触发内部时钟，仅需一个门延迟，并消除了电平转换需求，从而在低电压下实现低功耗和高性能。

💡 主要创新点

• 采用动态时钟发生器，从CLK输入到字线仅有一个门延迟，大幅提升速度。
• 所有关键路径电路使用VDDM域，无需电平转换，降低功耗并简化设计。

🏷 关键词

📄 原文摘要

Johnny Yang2, Hau-Tai Hsieh2, Frank Wu2, Jung-Ping Yang2, Atul Katoch3, Arun Achyuthan3, Donald Mikan1, Bryan Sheffield1, Jonathan Chang2 TSMC Design Technology, Austin, TX TSMC Design Technology, Hsinchu, Taiwan 3 TSMC Design Technology, Ottawa, Canada directly into a dynamic clock generator, which triggers the internal SRAM clock in the VDDM domain with just one gate delay. Since all circuits from the CLK input to the WL use VDDM, no level shifting is required and the WL is driven high as soon as possible. Signals driven by VDD-powered gates slow down dramatically at very low VDD levels. Hence, in order to retain the performance gain given by the HDR architecture, it is necessary for the tracking WL, BL and most of the circuits used to generate the sense-amplifier enable signal (in the control block) to be kept in the VDDM domain. 1 2 Mobile applications, such as smartphones streaming HD videos or virtual-reality

👥 作者与机构

Michael Clinton1, Hank Cheng2, HJ Liao2, Robin Lee2, Ching-Wei Wu2,