A 16Gb/s 3.6pJ/b Wireline Transceiver with Phase Domain Equalization Scheme: Integrated Pulse Width Modulation (iPWM) in 65nm CMOS

📋 论文概要

该论文提出了一种用于非对称链路（如内存接口和显示驱动器）的16Gb/s线缆收发器，采用集成脉冲宽度调制（iPWM）实现相位域均衡，在发射端完成全部均衡，从而简化接收端设计。相比传统分段FFE，该方案降低了功耗和面积开销，实现了3.6pJ/b的能效。

💡 主要创新点

• 提出相位域均衡（iPWM）方案，通过脉冲宽度调制在发射端实现均衡，无需传统多段FFE的大量分段和预驱动器。
• 发射端集成均衡功能，使接收端不需要或仅需少量均衡，适合非对称链路应用。
• 在维持恒定输出阻抗（50Ω）的同时，显著降低了功耗和芯片面积。

🏷 关键词

📄 原文摘要

Asymmetric links such as memory interfaces and display drivers require the transmitter to perform necessary equalization, while the receiver remains simple and has minimal or no equalization capability. Traditionally, FFE-based equalization techniques on power-efficient voltage-mode drivers have been used on the transmit end. Based on the FFE tap resolution requirement, the output driver and pre-driver are divided into multiple segments. Although such a segmented FFE implementation helps to maintain a constant output termination impedance (50Ω) across all tap settings, it comes at the cost of (a) increased signaling power, and (b) increased switching power since multiple segments are required to achieve desired linearity [1]. Phase domain equalization techniques, such as pulse width modulation (PWM), can equalize the channel without increasing signaling power or segmenting the output driver. However, PWM encoding requires the insertion

👥 作者与机构

Ashwin Ramachandran, Arun Natarajan, Tejasvi Anand

Oregon State University, Corvallis, OR