A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with Background Offset Calibration

📋 论文概要

该论文提出一种1-then-2b/cycle SAR ADC架构，通过后台校准技术解决多比特/周期结构中比较器失调和预充电延迟问题，实现了5mW低功耗和2.4GS/s高速采样。

💡 主要创新点

• 采用1-then-2b/cycle逐次逼近寄存器（SAR）ADC架构，在MSB转换中使用1位/周期以加快逻辑和DAC建立，后续使用2位/周期提高速度。
• 提出后台比较器失调校准方法，无需打断正常转换，有效补偿多比较器间的偏移误差。

🏷 关键词

📄 原文摘要

Wireless communication systems and Ethernet networks call for moderateresolution GS/s energy-efficient ADCs. While previous work [1] shows that the multi-bit per cycle SAR ADC can achieve low power due to various hardware reduction techniques, there are still a few limitations that restrain this architecture. First, the pre-charge slows down the logic and the DAC settling, especially during the MSB conversions. Second, unlike the offset among sub-channels of interleaving SAR ADCs, which can be easily calibrated in the background at the ADC backend [2], the offsets of the comparators in multi-bit SAR ADCs lead to a large sub-ranging error. Such offset is often calibrated in the foreground [1][3] but cannot track voltage and temperature (V&T) variations. This paper presents

👥 作者与机构

Chi-Hang Chan1, Yan Zhu1, Iok-Meng Ho1, Wai-Hong Zhang1,

Seng-Pan U1,2, Rui Paulo Martins1,3 University of Macau, Macao, China Synopsys Macau Ltd, Macao, China 3 Instituto Superior Tecnico/University of Lisboa, Lisboa, Portugal 1 2