An 8GS/s Time-Interleaved SAR ADC with Unresolved Decision Detection Achieving -58dBFS Noise and 4GHz Bandwidth in 28nm CMOS

📋 论文概要

该论文提出了一种8GS/s时间交织SAR ADC，通过未解决决策检测（URD）技术，利用XNOR门比较相邻比较器输出，若相同则产生URD标志并忽略后续决策，从而降低噪声并确保DAC建立时间。实现了-58dBFS的噪声和4GHz带宽，采用28nm工艺。

💡 主要创新点

• 提出未解决决策检测（URD）技术，通过XNOR门检测比较器输出是否一致，若一致则忽略后续决策，有效减少转换错误和噪声。
• 引入可编程延迟机制，确保在URD标志未触发时有足够时间让DAC稳定，提高时序鲁棒性。
• 采用时间交织SAR架构，在28nm工艺下实现8GS/s高速采样和4GHz带宽，兼顾低噪声性能。

🏷 关键词

📄 原文摘要

Bernd Wuppermann1, Charles Wu1, Cheongyuen W. Tsang1,3, Robert Neff1, Ken Nishimura1 Keysight Technologies, Santa Clara, CA 1 now with Apple, Cupertino, CA 3 now with Adecco, Mountain View, CA compared using an XNOR gate. If they are identical, then an unresolved decision (URD) flag is raised, causing this and subsequent decisions to be ignored when generating the ADC output code. The programmable delay is chosen to ensure that there remains sufficient time for the DAC to settle before the next comparator decision if the URD flag is not asserted. Since this detection operation is applied to the decision bits after conversion is complete, its own metastability rate can be made arbitrarily low by additional resampling at the 500MHz rate prior to the XNOR gate, while adding only latency to the ADC output. Skewed inverters with weak PMOS before and after the latches ensure that, even in the presence of noise

👥 作者与机构

John P. Keane1, Nathaniel J. Guilar1, Dusan Stepanovic1,2,