A 10b 1.5GS/s Pipelined-SAR ADC with Background Second-Stage Common-Mode Regulation and Offset Calibration in 14nm CMOS FinFET

📋 论文概要

本文提出了一种10位1.5GS/s的流水线SAR ADC，采用背景第二级共模调节和偏移校准技术，解决了高速SAR ADC中比较器噪声限制SNDR的问题，并在14nm CMOS工艺中实现。

💡 主要创新点

• 提出背景第二级共模调节技术，无需额外校准周期即可稳定共模电平。
• 实现背景偏移校准，降低比较器失调对性能的影响。
• 采用流水线SAR架构结合增益级，在高速下保持高SNDR。

🏷 关键词

📄 原文摘要

Alessandro Cevrero1, Ilter Ozkaya1, Thomas Toifl1 IBM Zurich Research Laboratory, Rueschlikon, Switzerland ETH Zurich, Zurich, Switzerland 1 2 High-speed SAR ADCs became popular with modern CMOS technologies because of their mostly digital logic, making them highly suitable for compact and powerefficient multi-GS/s time-interleaved ADCs. As many applications cannot tolerate input swings ≥1Vppd, comparator noise limits the SNDR of SAR ADCs, making gain stages necessary for higher SNDR – either as comparator pre-amplifiers or between pipelined stages. Pre-amplifiers significantly reduce the conversion speed of the ADC, but they provide maximum SNDR because linearity of the amplifier is irrelevant. An interstage amplifier for pipelining best suits mid-resolution SAR ADCs, where the required linearity is limited. Moreover, pipelining results in higher conversion speeds and power efficiency because the gain stage is used only once

👥 作者与机构

Lukas Kull1, Danny Luu1,2, Christian Menolfi1, Matthias Braendli1,

Pier Andrea Francese1, Thomas Morf1, Marcel Kossel1, Hazar Yueksel1,