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该论文提出了一种采用分数间隔前馈均衡器（FFE）的56Gb/s PAM-4发射机，在14nm CMOS工艺中实现，解决了PAM-4信号因垂直裕度减小而对残余码间干扰敏感的问题。通过优化均衡技术，实现了1.8pJ/b的低功耗和高数据率传输。
As data rates in electrical links rise to 56Gb/s, standards are gravitating towards PAM-4 modulation to achieve higher spectral efficiency. Such approaches are not without drawbacks, as PAM-4 signaling results in reduced vertical margins as compared to NRZ. This makes data recovery more susceptible to residual, or uncompensated, intersymbol interference (ISI) when the PAM-4 waveform is sampled by the receiver. To overcome this, existing standards such as OIF CEI 56Gb/s very short reach (VSR) require forward error correction to meet the target link BER of 1E-15. This comes at the expense of higher latency, which is undesirable for chip-to-chip VSR links in compute applications. Therefore, different channel equalization strategies should be considered for PAM-4 electrical links. Employing ½-UI (T/2) tap delays in an FFE extends the filter bandwidth as compared to baud- or T-spaced taps [1], resulting in improved timing margins
Timothy O. Dickson, Herschel A. Ainspan, Mounir Meghelli
IBM T. J. Watson Research Center, Yorktown Heights, NY