A 1V 7.8mW 15.6Gb/s C-PHY Transceiver Using Tri-Level Signaling for Post-LPDDR4

📋 论文概要

该论文提出了一种采用三电平C-PHY信令的收发器，用于后LPDDR4移动DRAM接口，在1V供电下实现15.6Gb/s数据速率和7.8mW功耗。解决了高速单端信令中SSN限制带宽以及差分信令引脚效率低的问题。

💡 主要创新点

• 采用C-PHY三电平信令，相比传统单端和差分信令，在高速下兼顾了高引脚效率和低SSN。
• 在1V低电压下实现了15.6Gb/s的高数据速率和7.8mW的低功耗，能效优异。

🏷 关键词

📄 原文摘要

smartphones and tablet PCs [1, 2]. Since mobile DRAM standard (LPDDR), for the next generation, targets the speed specification of 51.2GB/s, its I/O interface demands high bandwidth, low power and high efficiency. Single-ended signaling has been used for LPDDR interfaces due to 100% pin efficiency. However, as the data rate increases simultaneous switching noise (SSN) limits the bandwidth. Although differential signaling can effectively remove SSN, it suffers from a pin efficiency drop of 50%, requiring that the signal bandwidth be doubled. To address this issue, differential coding schemes that encode signals over multiple channels have been explored to achieve pin efficiency and SSN robustness [4]. This paper presents a 1V 15.6Gb/s C-PHY transceiver using tri-level signaling that consumes

👥 作者与机构

Woojun Choi1, Taewoong Kim1, Jongjoo Shim2, Hyungsoo Kim2,

Gunhee Han1, Youngcheol Chae1 Yonsei University, Seoul, Korea SK hynix, Icheon, Korea 1 2 Mobile DRAMs are essential to support memory-intensive operations for