← 返回论文列表 📄 下载原文 PDF  ISSCC 2017 · 20.5
ISSCC 2017Session 20 · DIGITAL VOLTAGE REGULATORS AND LOW-POWER TECHNIQUESDigital Circuits

A Dual-Symmetrical-Output Switched-Capacitor Converter with Dynamic Power Cells and Minimized Cross Regulation for Application Processors in 28nm CMOS of the regulation loop is much faster than that of power-cell allocation, stability is ensured. Each power cell consists of 2 flying capacitors and 8 power transistors and the VCR can be 2/3× or 1/2×. The configuration of each power cell is optimized to minimize the parasitic loss [6]. The channel selection switches, controlled by sel[n], connect the local output VOL to VO1 or VO2.

⚡ 本页包含 AI 生成的分析内容,仅供参考

📋 论文概要

提出了一种双对称输出开关电容转换器,采用动态功率单元和频率比较机制,通过自动调整功率单元来最小化交叉调节,适用于多输出电源管理。

💡 主要创新点

重要性
发表年份
ISSCC 2017

🏷 关键词

开关电容转换器双对称输出动态功率单元交叉调节频率比较

📄 原文摘要

and the power-cell shift register. First, the one-shot signals (ck1os and ck2os) control P1 and P2 to charge CC1 and CC2 for one clock period only. The ready signals (ready1 and ready2) are activated after charging is finished, and trigger the comparison between VF1 and VF2. After a short delay, CC1, CC2 and logic are reset. For the comparison, if VF1<VF2, meaning that f1>f2, the direction signal of the shift register is then set as direct=0, and the selection signals will shift left by one bit. This frequency adjustment repeats until f1 and f2 are very close to each other. The frequency comparator will then issue stop=1, and shifting will be terminated. To ensure accurate charging, the current sources and capacitors (CC1 and CC2) are well matched. For robust control, offsets are added to the comparators to form a hysteresis window. The whole process is driven solely by ck1 and ck2, without an

👥 作者与机构

Junmin Jiang1,2, Yan Lu1, Wing-Hung Ki2, Seng-Pan U1,3, Rui P. Martins1,4, Figure 20.5.3 shows the control logic that consists of the frequency comparator

分类:Digital Circuits · 年份:ISSCC 2017