A 3-to-10Gb/s 5.75pJ/b Transceiver with Flexible Clocking in 65nm CMOS

📋 论文概要

该论文提出了一种两步截断与消除方法，实现了高阶调制并避免了-1到1和1到-1的跳变，从而将数字控制延迟线(DCDL)的范围限制在CKHF的一个周期内。基于此设计了一种3-10Gb/s、能效5.75pJ/b的收发器，采用灵活时钟方案，在65nm CMOS工艺中实现了良好的抖动性能。

💡 主要创新点

• 提出两步截断与消除方法，避免高阶调制中的符号跳变，将DCDL范围限制在一个高频时钟周期内，简化了DCDL线性度设计。
• 通过精确匹配DCDL增益与TCKHF，实现ΔΣ截断误差的完美抵消，使MMD+DCDL组合成为真正的分数分频器，无需显式滤波，优化了MDLL的随机抖动性能。

🏷 关键词

📄 原文摘要

This 2-step truncation and cancellation method provides higher order modulation while avoiding -1 to 1 and 1 to -1 jumps, which limits the needed DCDL range to 1 cycle of CKHF, independent of output frequency/data rate. This restricted range eases design of the DCDL with good integral nonlinearity (INL). If the DCDL gain is exactly equal to TCKHF, ΔΣ truncation error is perfectly cancelled and the combination of the MMD+DCDL behaves as a true fractional divider [3]. Consequently, explicit filtering of the truncation error is unnecessary and the MDLL can be optimized for best RJ performance. 1 2 Serial link transceivers that can operate across a wide range of data rates offer flexibility and rapid realization of single-chip multi-standard solutions. The ability

👥 作者与机构

Romesh Kumar Nandwana1, Saurabh Saxena2, Ahmed Elkholy1,

Mrunmay Talegaonkar1, Junheng Zhu1, Woo-Seok Choi1, Ahmed Elmallah1, Pavan Kumar Hanumolu1 University of Illinois, Urbana, IL IIT Madras, Chennai, India error using a DCDL