A Transmitter and Receiver for 100Gb/s Coherent Networks with Integrated 4×64GS/s 8b ADCs and DACs in 20nm CMOS

📋 论文概要

该论文提出了一种用于100Gb/s相干网络的集成收发器，在20nm CMOS工艺中集成了4×64GS/s 8位ADC和DAC，解决了高速相干光通信中数据转换器与DSP集成的关键问题。

💡 主要创新点

• 首次在20nm CMOS中实现了4通道64GS/s 8位ADC和DAC的集成，支持双偏振QPSK调制。
• 通过精确的相位对齐技术，确保了XI、XQ、YI、YQ四通道之间的同步，实现了100Gb/s相干传输。

🏷 关键词

📄 原文摘要

Mehdi Khanpour, Kangmin Hu, Tamer Ali, Heng Zhang, Hairong Yu, Ben Rhew, Shiwei Sheng, Yonghyun Shim, Bo Zhang, Afshin Momtaz Broadcom, Irvine, CA At rates of 100Gb/s and above, CMOS DSP-based transceivers integrated with high-sampling-rate data converters are critical to realize the phase-sensitive modulation schemes based on coherent detection that are essential to metro and long-haul networks [1]. To support dual-polarization QPSK format, quad lowpower DACs and ADCs are needed and precise phase alignment has to be maintained between XI, XQ, YI, and YQ channels, in order to transmit and extract the phase information in the coherent system, as shown in Fig. 29.2.1. For longhaul transmission at 100Gb/s, because of the FEC overhead, the baud rate per channel can be as high as 32Gb/s. In addition, the receiver often requires double sampling at 64GS/s for robust clock-data recovery and SNR improvement for

👥 作者与机构

Jun Cao, Delong Cui, Ali Nazemi, Tim He, Guansheng Li, Burak Catli,