A 673μW 1.8-to-2.5GHz Dividerless Fractional-N Digital PLL with an Inherent Frequency-Capture Capability and a Phase-Dithering Spur Mitigation for IoT Applications

📋 论文概要

该论文提出了一种无分频器的分数N数字PLL，工作频率1.8-2.5GHz，功耗仅673μW，具有固有的频率捕获能力，解决了超低功耗IoT收发器中本地振荡器的高能耗问题。

💡 主要创新点

• 采用无分频器架构，消除了传统PLL中分频器的功耗和噪声，实现低功耗。
• 提出固有频率捕获机制，无需额外锁定辅助电路，简化设计并降低功耗。
• 全数字实现，面积小，适合IoT应用的成本敏感需求。

🏷 关键词

📄 原文摘要

Belgium 1 2 The Internet-of-Things (IoT) is gaining momentum, and the ultra-low-power (ULP) RF transceiver is one of the key enablers. Generation of the local oscillator (LO) consumes a significant share of the total energy of these ULP transceivers which are typically powered by small batteries. Therefore, a fractional-N PLL needs to perform LO frequency synthesis and modulation with a very stringent power budget, i.e., below 1mW [1]. A digital PLL is favored in these applications because of the benefit of small area, which is also a critical cost consideration in IoT. On the other hand, the LO quality generated by these ULP PLLs cannot be compromised, and it needs to fulfil the RF requirements defined in the IoT

👥 作者与机构

Yuming He1, Yao-Hong Liu1, Takashi Kuramochi2, Johan van den Heuvel1,

Benjamin Busze1, Nereo Markulic3, Christian Bachmann1, Kathleen Philips1 Holst Centre / imec, Eindhoven, The Netherlands Rohm Semiconductor, Dusseldorf, Germany 3 imec, Heverlee,