A 100nA-to-2mA Successive-Approximation Digital LDO with PD Compensation and Sub-LSB Duty Control Achieving a 15.1ns Response Time at 0.5V

📋 论文概要

该论文提出了一种基于逐次逼近的数字低压差稳压器（DLDO），通过PD补偿和亚LSB占空比控制技术，实现了从100nA到2mA的宽负载电流范围，并达到15.1ns的快速瞬态响应，解决了传统模拟LDO在低输入电压下无法工作的问题。

💡 主要创新点

• 采用逐次逼近架构实现数字LDO，结合PD补偿技术提高环路稳定性。
• 引入亚LSB占空比控制，实现精细的电压调节和低纹波输出。

🏷 关键词

📄 原文摘要

Modern subthreshold SoC designs feature multiple power domains to dynamically track the maximum energy-efficiency point (0.32-0.45V [1]) in response to application demands. While analog low-drop-out (LDO) regulators have shown rapid response times (e.g. TR = 0.65ns [2]) and excellent steady-state performance, they fail to operate at the low input voltages, VIN, typically supplied to such SoCs via either a high-efficiency switching DC-DC converter or an external harvesting source (e.g., VIN = 0.5V). On the other hand, digital LDOs (DLDOs) are becoming popular in low-voltage SoC designs where they can operate reliably from supplies down to 0.5V. However, conventional DLDOs respond slowly to large current steps, especially at low voltages (e.g., TR = ~44ns, 57.1ns, and 4μs at VIN=1V [3-5], and 20μs at VIN=0.5V [1]). Furthermore, they suffer from limited dynamic range over which the load is regulated and stable (e.g. < 50× [1,4,5])

👥 作者与机构

Loai G. Salem, Julian Warchall, Patrick P. Mercier

University of California, San Diego, CA