A 7nm 256Mb SRAM in High-K Metal-Gate FinFET Technology with Write-Assist Circuitry for Low-VMIN Applications

📋 论文概要

本文针对7nm FinFET工艺下随机Vt变化和布线电阻电容增加导致的SRAM写操作难度问题，提出了一种写辅助电路以降低最小工作电压（Vmin）。通过采用高k金属栅极FinFET技术，实现了256Mb SRAM的低Vmin应用，适用于电池供电移动设备。

💡 主要创新点

• 提出适用于7nm FinFET工艺的写辅助电路，有效降低SRAM的写入最小工作电压（Vmin）。
• 在高k金属栅极FinFET技术中集成256Mb SRAM，同时满足面积缩放和低功耗需求。
• 针对先进工艺下随机阈值电压变化和互连寄生效应，优化了SRAM阵列和外围电路设计。

🏷 关键词

📄 原文摘要

Hank Cheng1, Hidehiro Fujiwara1, Jih-Yu Lin1, Kao-Cheng Lin1, John Hung1, Robin Lee1, Hung-Jen Liao1, Jhon-Jhy Liaw2, Quincy Li2, Chih-Yung Lin2, Mu-Chi Chiang2, Shien-Yang Wu2 TSMC Design Technology, Hsinchu, Taiwan TSMC, Hsinchu, Taiwan 1 2 The growing demand for battery powered mobile devices is a major driver for reducing power and continued area scaling in SOC chips. Continued scaling of the transistor and metal interconnection geometry is accompanied by increasing random Vt variation and increased wire routing resistance and capacitance variation in advanced technologies. Such variation degrades SRAM performance and its minimum operating voltage, which then seriously impact the battery life of mobile devices. FinFET technology provides a superior short-channel effect and less random dopant fluctuation. However, the quantized channel width and length force constrains on transistor sizing of high density SRAM bitcells. Figure

👥 作者与机构

Jonathan Chang1, Yen-Huei Chen1, Wei-Min Chan1, Sahil Preet Singh1,