develop methodologies for fully automated digital design of key analog building blocks. The phase-locked loop (PLL) is a block for which an all-digital implementation has been sought recently. There have been several approaches for fully synthesized digital PLLs [1-4] via gate-level implementation of a digitally controlled oscillator (DCO) and a time-to-digital converter (TDC). Though automated layout has been achieved, the lock-range and phase-noise performance are subject to process variations. Critical performancelimiting blocks, such as the TDC and DCO, should be carefully designed with analog circuit simulators, diluting the inherent benefits of digital design. This work presents a highly programmable and synthesizable TDC- and DCO-less fractionalN PLL architecture, employing a phase-locked direct-digital
Hwasuk Cho1, Kihwan Seong1, Kwang-Hee Choi2, Jin-Hyeok Choi2,
Byungsub Kim1, Hong-June Park1, Jae-Yoon Sim1 Pohang University of Science and Technology, Pohang, Korea Samsung Electronics, Hwaseong, Korea 1 2 There continue to be efforts to