An Output-Capacitor-Free Analog-Assisted Digital Low-Dropout Regulator with Tri-Loop Control

📋 论文概要

该论文提出了一种无输出电容的模拟辅助数字低压差稳压器（LDO），采用三环控制架构，解决了传统数字LDO需要大输出电容且响应慢的问题，实现了快速瞬态响应和面积节省。

💡 主要创新点

• 提出模拟辅助数字控制架构，结合模拟环路的快速响应和数字环路的精确调节能力，实现无输出电容的LDO设计。
• 采用三环控制策略（包括快速模拟环路、慢速数字环路和自适应环路），在负载跳变时快速稳定输出电压，同时保持低静态功耗。

🏷 关键词

📄 原文摘要

now with South China University of Technology, Guangzhou, China 2 Synopsys Macau Ltd, Macao, China Instituto Superior Tecnico, Universidade de Lisboa, Portugal 3 4 Low-dropout regulators (LDOs) are widely distributed in SoC designs to supply individual voltage domains, and a digital LDO (DLDO) is favorable for its lowvoltage operation and process scalability. However, as many SoCs generate a load current (ILOAD) variation at sub-A/ns level, voltage regulators require a large areaconsuming output capacitor (COUT) to maintain the output voltage (VOUT) during fast transients. A conventional shift-register (SR)-based DLDO [1] suffers from a power and speed trade-off, thus requires a large COUT. To break the tie and minimize COUT, [2-5] applied coarse-fine tuning and adaptive clocking, but a fast sampling clock is still necessary for instantaneous VOUT sensing. Event-driven control used in [6] reacts fast within one clock cycle, but the ADC (with 7

👥 作者与机构

Mo Huang1,2, Yan Lu1, Seng-Pan U1,3, Rui P. Martins1,4

University of Macau, Macau, China