A 0.0049mm2 2.3GHz Sub-Sampling Ring-Oscillator PLL with Time-Based Loop Filter Achieving -236.2dB Jitter-FOM

📋 论文概要

该论文提出了一种基于环形振荡器的子采样锁相环，并采用时间域环路滤波器，实现了极小的芯片面积（0.0049mm²）和低抖动性能（抖动FOM为-236.2dB），解决了传统环形振荡器PLL面积大、相位噪声差的问题。

💡 主要创新点

• 采用子采样技术结合环形振荡器，大幅降低面积并保持低抖动
• 引入时间域环路滤波器替代传统模拟环路滤波器，进一步减小面积并改善噪声性能
• 在2.3GHz工作频率下实现了-236.2dB的抖动FOM，达到与LC振荡器PLL相当的性能水平

🏷 关键词

📄 原文摘要

High-performance phase-locked loops (PLLs) and clock multipliers with low jitter/phase noise are essential for numerous applications, such as digital microprocessors and SoCs, wireline/optical links, data converters and wireless radios. Given the increasing cost per unit area of advanced CMOS nodes and the need for a multitude of PLLs in complex digital systems, there is a need to miniaturize the area of PLLs while not sacrificing jitter and phase noise performance. Ring oscillators are extremely compact when compared with their LC counterparts, but exhibit typically 15-to-20dB worse phase noise performance. A conventional analog charge-pump PLL that exploits a passive loop filter can be low-noise but requires a large loop-filter capacitor for frequency compensation, which dominates the area in a ring-oscillator PLL. An analog sub-sampling PLL

👥 作者与机构

Jeffrey (Tsung-Hao) Chuang, Harish Krishnaswamy

Columbia University, New York, NY