Improved Power-Side-Channel-Attack Resistance of an AES-128 Core via a Security-Aware Integrated Buck Voltage Regulator

📋 论文概要

本文提出一种安全感知的集成降压稳压器，用于提高AES-128加密核心对电源侧信道攻击（如DPA和CPA）的抵抗能力。通过带宽限制的集成低压差稳压器、多相开关电容稳压器以及相随机化等技术，实现了数据无关的电源电流模式，从而有效抵御侧信道攻击。

💡 主要创新点

• 首次将集成降压稳压器与安全设计相结合，通过稳压器的带宽限制和相随机化技术，在不显著增加面积和功耗的情况下，显著提升加密核心的侧信道攻击抵抗能力。
• 提出一种多相开关电容电压调节器架构，结合相位随机化，能够有效平滑电源电流的统计特性，使得攻击者难以从电源侧提取密钥信息。
• 实现了对AES-128核心的完整集成方案，并在实际芯片中验证了其对抗DPA/CPA攻击的有效性，优于传统的电路级防御方法。

🏷 关键词

📄 原文摘要

g. Differential Power Analysis (DPA) and Correlation Power Analysis (CPA), are major threats to the security of crypto engines in SoC platforms. Circuit-level SCA countermeasures to achieve dataindependent supply current patterns via implementation of crypto engines using non-conventional logic (complemented [1] or charge recovery [2]) and local switched-capacitor-based supply current equalization [3] have been demonstrated. The feasibility of using bandwidth-limited integrated low dropout regulators, multi-phase switched-capacitor VRs with phase-randomization and integrated inductive voltage regulators (IVR) to enhance PSCA resistance have been explored before via simulation studies [4]. In this paper, we demonstrate improved PSCA resistance offered by an on-die all-digital high-frequency IVR in

👥 作者与机构

Monodeep Kar1, Arvind Singh1, Sanu Mathew2, Anand Rajan2, Vivek De2, Saibal Mukhopadhyay1

Georgia Institute of Technology, Atlanta, GA Intel, Hillsboro, OR 1 2 Power side-channel attacks (PSCA), e