A 12b 330MS/s Pipelined-SAR ADC with PVTStabilized Dynamic Amplifier Achieving <1dB SNDR Variation

📋 论文概要

该论文提出了一种12位330MS/s的流水线逐次逼近型模数转换器，采用PVT稳定的动态放大器，实现了小于1dB的信噪失真比变化，解决了传统运算放大器在高速流水线ADC中功耗高的问题。

💡 主要创新点

• 提出了一种PVT稳定的动态放大器，通过偏置电流和电容的自动校准，在工艺、电压和温度变化下保持增益和带宽稳定。
• 采用动态放大器替代传统运算放大器，利用摆率更高效的特性，在相同偏置电流下将建立时间缩短至约四分之一。
• 在流水线SAR ADC架构中集成动态放大器，实现了低功耗和高线性度，并显著降低了SNDR随PVT的变化。

🏷 关键词

📄 原文摘要

Texas Instruments, Dallas, TX 1 2 In high-speed pipeline or pipelined-SAR ADCs, conventional opamp-based residue amplifiers consume significant amounts of power due to stringent settling speed and accuracy requirements. A recent alternative approach employs a dynamic amplifier [1] to achieve a more efficient form of settling, stemming from the fact that slewing is more power efficient than exponential settling (Fig. 28.4.1). For example, at 6b accuracy, the setting time of a dynamic amplifier is about a quarter of that of a conventional opamp (non-slewing) with the same bias current. However, the efficiency of the dynamic amplifier is accompanied by a few undesirable features such as ill-defined gain, and PVT and clock jitter sensitivity. In particular, as the voltage gain of a dynamic amplifier relates to the non-constant transconductance, load capacitance and slewing time (gmA, CLA and tA,

👥 作者与机构

Hai Huang1, Sudipta Sarkar1, Brian Elies2, Yun Chiu1

University of Texas at Dallas, Richardson, TX