A 2.5-to-5.75GHz 5mW 0.3psrms-Jitter Cascaded Ring-Based Digital Injection-Locked Clock Multiplier in 65nm CMOS

📋 论文概要

该论文提出了一种基于级联环的数字注入锁定时钟倍频器，在65nm CMOS工艺下实现了2.5-5.75GHz的频率范围、5mW功耗和0.3ps rms抖动。通过边缘替换技术有效抑制环形振荡器噪声，解决了传统PLL噪声抑制带宽受限的问题。

💡 主要创新点

• 采用级联环结构实现数字注入锁定，提高了噪声抑制带宽并降低了抖动。
• 在低功耗（5mW）下实现了宽频率范围（2.5-5.75GHz）和低抖动（0.3ps rms），优于传统PLL方案。

🏷 关键词

📄 原文摘要

traditionally used for clocking digital systems such as processors. While they are most commonly implemented using PLLs, it is becoming increasingly difficult to design them in a power efficient manner, as their jitter requirements grow more stringent. Recognizing that the main limitation of PLLs arises from limited RO noise suppression bandwidth (NBW = FREF/10), multiplying delay-locked loops (MDLLs) that suppress noise by replacing a RO’s noisy edge with a clean reference clock edge have gained prominence [1-3]. Such an edge replacement operation suppresses RO noise with an increased NBW of about FREF/4 [1]. However, imperfections of edge replacement logic have limited the output frequency of MDLLs [1, 2] or degraded their jitter performance at frequencies beyond 2.5GHz [3]. Furthermore, MDLLs

👥 作者与机构

Daniel Coombs, Ahmed Elkholy, Romesh Kumar Nandwana,

Ahmed Elmallah, Pavan Kumar Hanumolu University of Illinois, Urbana, IL Ring oscillator (RO)-based clock multipliers are