A Time-Based Receiver with 2-tap DFE for a 12Gb/s/pin Single-Ended Transceiver of Mobile DRAM Interface in 0.8V 65nm CMOS

📋 论文概要

该论文提出了一种基于时间的接收器（time-based receiver），并集成了2抽头判决反馈均衡器（DFE），用于移动DRAM接口的低电压单端收发器。在0.8V 65nm CMOS工艺下，实现了12Gb/s/pin的数据率，解决了低供电电压下高速率接收的难题。

💡 主要创新点

• 提出基于时间的接收器架构，利用时间域处理替代传统电压域处理，提升低电压下的接收速度。
• 集成2抽头DFE，有效补偿信道损耗，在0.8V低电压下实现12Gb/s/pin单端传输。

🏷 关键词

📄 原文摘要

Single-ended transceivers are mostly used for DRAM interfaces to reduce pin count. A low-supply transceiver is preferred, especially for mobile DRAM interfaces, for low-power consumption while maintaining a high-speed interface for transmission of image data [1]. To reduce transmitter power in single-ended transceivers, both the supply voltage and the signal swing are reduced: 0.8V and 200mV, or below [2]. However, with a small signal swing the low-supply voltage limits the maximum data rate that can be handled by the receiver (RX); the maximum data rate reported is below 10Gb/s with a supply voltage of 0.8V in 65nm CMOS [2-4]. In a conventional RX at a low-supply voltage, the maximum data rate is limited by the small gm/C of the RX front-end circuit. To eliminate this

👥 作者与机构

Il-Min Yi1, Min-Kyun Chae1, Seok-Hun Hyun2, Seung-Jun Bae2,

Jung-Hwan Choi2, Seong-Jin Jang2, Byungsub Kim1, Jae-Yoon Sim1, Hong-June Park1 Pohang University of Science and Technology, Pohang, Korea Samsung Electronics, Hwasung, Korea 1