Adaptive Clocking in the POWER9TM Processor for Voltage Droop Protection

📋 论文概要

该论文介绍了POWER9处理器中用于电压降保护的适应性时钟策略，通过嵌入模拟电压降监视器（VDM）来指导数字锁相环（PLL）调整时钟频率，从而减少电压降事件所需的时序裕量。

💡 主要创新点

• 提出了一种基于模拟电压降监视器的适应性时钟架构，能够实时检测电压降并动态调整时钟频率。
• 通过减少电压降事件所需的时序裕量，提高了处理器的性能和能效。

🏷 关键词

📄 原文摘要

Pawel Owczarczyk3, Eric J. Fluhr1, Joshua Friedrich1, Paul Muench3, Timothy Diemoz3, Pierce Chuang2, Christos Vezyrtzis2 IBM, Austin, TX IBM, Yorktown Heights, NY 3 IBM, Poughkeepsie, NY 1 2 Increasing transistor counts in modern processors can create instantaneous changes in current, driving nanosecond-speed supply voltage (VDD) droops that require extra guardband for correct product operation. The POWER9 processor uses an adaptive clock strategy to reduce timing margin needed during power supply droop events by embedding analog voltage-droop monitors (VDMs) that direct a digital phase-locked loop (DPLL) to immediately reduce clock frequency in response. The POWER9 chip contains 24 cores organized into 6 structures called Quads, each containing 5 power domains, consisting of 4 cores and a cache region, whose clock grids all share a DPLL. As seen in Fig. 26.5.1, a voltage sense point from each domain is sampled (solid lines) by each of the 5 VDMs, whose outputs

👥 作者与机构

Michael S. Floyd1, Phillip J. Restle2, Michael A. Sperling3,