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ISSCC 2017Session 20 · DIGITAL VOLTAGE REGULATORS AND LOW-POWER TECHNIQUESDigital Circuits

A 13.8µW Binaural Dual-Microphone Digital ANSI S1.11 Filter Bank for Hearing Aids with Zero-ShortCircuit-Current Logic in 65nm CMOS

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📋 论文概要

该论文提出了一种用于双耳助听器的ANSI S1.11 1/3倍频程滤波器组芯片,支持每耳双麦克风。通过采用电荷恢复逻辑设计,在约1MHz的低时钟频率下实现了13.8µW的超低功耗,解决了双耳多麦克风系统计算和功耗需求高的问题。

💡 主要创新点

核心指标
13.8µW功耗
重要性
发表年份
ISSCC 2017

🏷 关键词

双耳助听器滤波器组电荷恢复逻辑低功耗ANSI S1.11

📄 原文摘要

This paper presents an ANSI S1.11 1/3-octave filter-bank chip for binaural hearing aids with two microphones per ear. Binaural multimicrophone systems significantly suppress noise interference and preserve interaural time cues at the cost of significantly higher computational and power requirements than monophonic single-microphone systems. With clock rates around the 1MHz mark, these systems are ideal candidates for low-power implementation through chargerecovery design. At such low clock frequencies, however, charge-recovery logic suffers from short-circuit currents that limit its theoretical energy efficiency [1]. The chip described in this paper is designed in 65nm CMOS using a new chargerecovery logic, called zero-short-circuit-current (ZSCC) logic, that drastically reduces short-circuit current. It processes 4 input streams at 1.75MHz with a charge recovery rate of 92%, achieving 9.7× lower power per input compared

👥 作者与机构

Hsi-Shou Wu, Zhengya Zhang, Marios C. Papaefthymiou

University of Michigan, Ann Arbor, MI

分类:Digital Circuits · 年份:ISSCC 2017