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本文提出了一种9GS/s、1GHz带宽的过采样连续时间流水线ADC，通过连续时间环路滤波器替代离散时间前端，解决了传统开关电容前端带来的混叠、噪声折叠和高峰值驱动电流问题，实现了-161dBFS/Hz的噪声谱密度。
front-end by a switchedcapacitor circuit and all internal signals are processed in discrete-time (DT) even though the front-end sampler introduces artifacts such as aliasing, noise folding, and high-peak ADC driving current to charge the input sampling capacitor. In ΔΣ ADCs, those issues are resolved by replacing the DT loop filter with a continuoustime (CT) implementation which relaxes the pre-filter and driver requirements in the signal chain thus reducing the overall signal chain power consumption. CTΔΣs also introduce additional benefits such as 2-3× higher clocking capability in the same process node and low-power internal opamps due to relaxed noise, loading, and gain bandwidth requirements. Since these CT benefits are not exclusive to the ΔΣ architecture, other ADC architectures could similarly benefit by replacing
Hajime Shibata1, Victor Kozlov1, Zexi Ji1, Asha Ganesan2, Haiyang Zhu2, Donald Paterson2
Analog Devices, Toronto, Canada Analog Devices, Wilmington, MA 1 2 In traditional ADCs the input signal is sampled at the