A 60Gb/s 288mW NRZ Transceiver with Adaptive Equalization and Baud-Rate Clock and Data Recovery in 65nm CMOS Technology

📋 论文概要

本文提出了一款在65nm CMOS工艺下实现的60Gb/s NRZ收发器，功耗仅288mW，能效为4.8pJ/b。该收发器采用自适应均衡和波特率时钟数据恢复技术，解决了超高速有线通信中数据率提升与功耗约束之间的矛盾。

💡 主要创新点

• 在65nm CMOS工艺中实现了60Gb/s的NRZ收发器，相比之前28-40nm工艺的56.5Gb/s设计，在更老工艺下达到更高数据率。
• 采用自适应均衡技术，能够根据信道特性自动调整均衡参数，提升信号完整性。
• 采用波特率时钟数据恢复（CDR）架构，降低时钟频率和功耗，同时保持高速数据恢复能力。

🏷 关键词

📄 原文摘要

Qualcomm Atheros, San Jose, CA 1 2 The demand for ultra-high speed transceivers continues to explode, and while the data-rate for high-speed I/O standards has increased accordingly, the historically constant or even decreasing power budgets available for the transceivers push these designs to be extremely energy efficient. To begin addressing this need, recently published NRZ transceivers operating up to 56.5Gb/s with a 1-tap DFE and/or CTLE [1,2] in 28-40nm CMOS processes have been demonstrated for <20dB loss channels with energy efficiencies ranging from 4.4 to 11.96pJ/b. In order to support channels with higher losses, the half-rate 65nm receiver frontend design described in [3] includes a 3-tap DFE, a 2-tap FFE, and a CTLE at ~2.88pJ/b, but neither closed-loop equalizer adaptation nor clock and data recovery were demonstrated. Closing these loops is especially critical in such an interleaved architecture, since at these data-rates each interleaved datapath can

👥 作者与机构

Jaeduk Han1, Yue Lu2, Nicholas Sutardja1, Elad Alon1

University of California, Berkeley, CA