A 0.42ps-Jitter -241.7dB-FOM Synthesizable Injection-Locked PLL with Noise-Isolation LDO

📋 论文概要

该论文提出了一种基于噪声隔离LDO的可综合注入锁定PLL，通过离散时间LDO实现时移操作，隔离PLL免受电源和LDO噪声影响，从而在噪声SoC环境中保持鲁棒性。在65nm CMOS工艺下，采用标准单元库和数字设计工具实现，在0.9GHz振荡频率下实现了0.42ps抖动和3.8mW功耗。

💡 主要创新点

• 提出噪声隔离LDO，采用离散时间操作实现时移，有效隔离PLL与电源及LDO噪声。
• 完全使用标准单元库和数字设计工具实现PLL核心布局，实现可综合设计。
• 在可综合PLL中实现了0.42ps的低抖动性能，同时保持低功耗。

🏷 关键词

📄 原文摘要

(ILPLL), using a noise-isolation LDO. The noise-isolation LDO realizes a time-shift operation to isolate the PLL from both supply and LDO noise, so the IL-PLL operation remains robust, even within a noisy SoC. The core layout of the PLL is implemented using solely a foundry provided standard-cell library for a 65nm CMOS process with standard digital design tools. Among synthesizable PLLs, jitter performance of 0.42ps is achieved with 3.8mW power consumption at 0.9GHz oscillation. Figure 8.5.1 shows a comparison between a common continuous-time (CT) LDO and the proposed discrete-time (DT) LDO. A conventional synthesizable PLL [15] has no supply regulation by the LDO, so it may potentially experience a frequency jump when faced with a sudden supply-voltage change. It is relatively

👥 作者与机构

Huy Cu Ngo, Kengo Nakata, Toru Yoshioka, Yuki Terashima,

Kenichi Okada, Akira Matsuzawa Tokyo Institute of Technology, Tokyo, Japan This paper presents a supply regulated synthesizable injection-locked PLL