A 60pJ/b 300Mb/s 128×8 Massive MIMO Precoder-Detector in 28nm FD-SOI

📋 论文概要

本文提出一种基于28nm FD-SOI工艺的128×8大规模MIMO预编码-检测器基带芯片，在1.1mm²面积上实现了300Mb/s吞吐率和60pJ/b能效，相比传统小规模MIMO面积降低53%以上，解决了大规模MIMO芯片面积和功耗过大的问题。

💡 主要创新点

• 实现了128×8大规模MIMO预编码-检测器芯片，面积和功耗大幅降低，上行链路面积减少53%，下行减少17%。
• 通过算法优化和高度灵活的设计框架，在保持性能的同时大幅提升能效，达到60pJ/b。
• 获得12dB阵列增益和2倍空间复用增益，有效提升通信系统容量和可靠性。

🏷 关键词

📄 原文摘要

Further exploitation of the spatial domain, as in Massive MIMO (MaMi) systems, is imperative to meet future communication requirements [1]. Up-scaling of conventional 4×4 small-scale MIMO implementations to MaMi is prohibitive interms of flexibility, as well as area and power cost. This work discloses a 1.1mm2 128×8 MaMi baseband chip, achieving up to 12dB array and 2× spatial multiplexing gains. The area cost compared to previous state-of-the-art MIMO implementations [2-3], is reduced by 53% and 17% for up- and down-link, respectively. Algorithm optimizations and a highly flexible framework were evaluated on real measured channels. Extensive hardware time multiplexing lowered area cost, and leveraging on flexible FD-SOI body bias and clock gating resulted in an energy efficiency of 6.56nJ/QRD and 60pJ/b at 300Mb/s detection rate. For the downlink, pre-coding is a highly critical task in terms of functionality and

👥 作者与机构

Hemanth Prabhu, Joachim Neves Rodrigues, Liang Liu, Ove Edfors

Lund University, Lund, Sweden