An 8-Channel 4.5Gb 180GB/s 18ns-Row-Latency RAM for the Last Level Cache

📋 论文概要

本文提出了一款8通道4.5Gb容量的DRAM，用于最后一级缓存，实现了180GB/s的高带宽和18ns的低行延迟。通过多通道架构和优化的电路设计，解决了多核CPU和GPU对内存性能的迫切需求。

💡 主要创新点

• 采用8通道并行架构，显著提升带宽至180GB/s。
• 优化行延迟至18ns，满足最后一级缓存的低延迟要求。
• 针对缓存应用场景，在DRAM设计中实现了高吞吐量与低延迟的平衡。

🏷 关键词

📄 原文摘要

Chun-Peng Wu1, Chun-Kai Wang1, Chun-Wei Lo1, Li-Chin Tien1, Der-Min Yuan1, Yung-Ching Hsieh1, Jenn-Shiang Lai2, Wen-Pin Hsu2, Chien-Chih Huang2, Chi-Kang Chen2, Yung-Fa Chou2, Ding-Ming Kwai2, Zhe Wang3, Wei Wu3, Shigeki Tomishima3, Pat Stolt3, Shih-Lien Lu4 Piecemakers Technology, Hsinchu, Taiwan ITRI, Hsinchu, Taiwan 3 Intel, Hilsboro, OR 4 TSMC, Hsinchu, Taiwan 1 2 In recent years, the demand for memory performance has grown rapidly due to the increasing number of cores on a single CPU, along with the integration of graphics processing units and other accelerators. Caching has been a very effective way to relieve bandwidth demand and to reduce average memory latency. As shown by the cache feature table in Fig. 23.9.1, there is a big latency gap between SRAM caches in the CPU and the external DRAM main memory. As a key element for future computing systems, the last level cache (LLC) should have

👥 作者与机构

Tah-Kang Joseph Ting1, Gyh-Bin Wang1, Ming-Hung Wang1,