A 4Gb LPDDR2 STT-MRAM with Compact 9F2 1T1MTJ Cell and Hierarchical Bitline Architecture

📋 论文概要

本文提出了一款4Gb LPDDR2接口的STT-MRAM芯片，采用紧凑的9F2 1T1MTJ存储单元和分层位线架构，解决了高密度与高速读写之间的矛盾，实现了非易失性存储器的性能提升。

💡 主要创新点

• 提出9F2尺寸的1T1MTJ存储单元，相比传统单元面积更小，有利于提高存储密度。
• 采用分层位线架构，优化了读写路径，降低了延迟和功耗。

🏷 关键词

📄 原文摘要

Jihyae Bae1, Tsuneo Inaba2, Hiromi Noro2, Hyunin Moon1, Sungwoong Chung1, Kazumasa Sunouchi2, Jinwon Park1, Kiseon Park1, Akihito Yamamoto2, Seoungju Chung1, Hyeongon Kim1, Hisato Oyamatsu2, Jonghoon Oh1 SK hynix Semiconductor, Icheon, Korea Toshiba Electronics Korea, Seoul, Korea 1 2 Spin-transfer torque magnetic RAM (STT-MRAM) is one of the most promising nonvolatile memories with guaranteed high-speed read and write operations. Along with performance improvements in the tunnel magnetoresistance (TMR) and the magnetic tunnel junction’s (MTJ) required switching current, there have also been reports on high-capacity (up to tens of Mb) STT-MRAM [1-4]. In [2] a perpendicular-TMR (pMTJ) device is used to reduce the switching current and a high-speed current sense amplifier is proposed. In [3] a 54nm 2T-1MTJ 14F2-cell is proposed that uses a high-density DRAM process: self-aligned contact and plug

👥 作者与机构

Kwangmyoung Rho1, Kenji Tsuchida2, Dongkeun Kim1, Yutaka Shirai2,