A 7nm FinFET SRAM Macro Using EUV Lithography for Peripheral Repair Analysis

📋 论文概要

该论文提出了一款采用极紫外（EUV）光刻技术制造的7nm FinFET SRAM宏单元，并针对外围电路修复进行了分析。通过使用EUV减少光刻步骤数量，提升了工艺效率。

💡 主要创新点

• 首次在7nm FinFET SRAM宏中应用EUV光刻技术，减少传统多重图案化步骤。
• 针对SRAM外围电路实现了修复分析，提升良率。

🏷 关键词

📄 原文摘要

Changnam Park, Minsun Hong, Giyong Yang, Jeongho Do, Jinyoung Lim, Seungyoung Lee, Ingyum Kim, Sanghoon Baek, Jonghoon Jung, Daewon Ha, Hyungsoon Jang, Taejung Lee, Chul-Hong Park, Bongjae Kwon, Hyuntaek Jung, Sungwee Cho, Yongjae Choo, JaeSeung Choi Samsung Electronics, Hwasung, Korea Conventional patterning techniques, such as self-aligned double patterning (SADP) and litho-etch-litho-etch (LELE), have paved the way for the extreme ultraviolet (EUV) technology that aims to reduce the photomask steps [1,2]. EUV adds the extreme scaling to the high-performance of FinFET technology, thus opening up new opportunities for system-on-chip designers: delivering power, performance, and area (PPA) competitiveness. In terms of area, peripheral logic has scaled down aggressively in comparison to the bitcell given the intense design-rule shrinkage. Figure 12.2.1 shows the bitcell scaling trend and the

👥 作者与机构

Taejoong Song, Hoonki Kim, Woojin Rim, Yongho Kim, Sunghyun Park,