A 28Gb/s Digital CDR with Adaptive Loop Gain for Optimum Jitter Tolerance

📋 论文概要

本文提出一种28Gb/s数字时钟数据恢复(CDR)电路，采用自适应环路增益技术以优化抖动容限。针对Bang-Bang相位检测器增益随输入抖动变化导致环路增益不稳定的问题，通过检测抖动幅度动态调整环路增益，提高了CDR对PVT变化、串扰和电源噪声的鲁棒性。

💡 主要创新点

• 提出自适应环路增益机制，根据输入抖动幅度动态调整数字CDR的环路增益，解决了Bang-Bang相位检测器增益对抖动敏感的问题。
• 实现了28Gb/s高速率下的最优抖动容限，无需额外校准或模拟电路，仅通过数字逻辑实现自适应控制。

🏷 关键词

📄 原文摘要

(CDR) circuits becomes increasingly important in maintaining low bit error rates (BER) in wireline links. Digital CDRs are popular in part for their robustness, but their use of bang-bang phase detectors (BB-PD) makes their performance sensitive to changes in jitter caused by PVT variations, crosstalk or power supply noise. This is because the gain of a BB-PD depends on the CDR input jitter, causing the loop gain of the CDR to change if the jitter magnitude or spectrum varies. This problem is illustrated in Fig. 6.7.1 where small jitter leads to excessive loop gain and hence to an underdamped behaviour in the CDR jitter tolerance (JTOL), while large jitter leads to insufficient loop gain and hence to low overall JTOL. To prevent this, we propose a CDR with an adaptive loop gain, KG, as shown

👥 作者与机构

Joshua Liang1, Ali Sheikholeslami1, Hirotaka Tamura2, Yuuki Ogata2, Hisakatsu Yamaguchi2

University of Toronto, Toronto, Canada Fujitsu Laboratories, Kawasaki, Japan 1 2 As we move to higher data rates, the performance of clock and data recovery