A 14nm 1GHz FPGA with 2.5D Transceiver Integration

📋 论文概要

该论文介绍了一款采用14nm工艺制造的FPGA系列，通过2.5D封装技术将可编程逻辑芯片与28Gb/s收发器芯片集成在一起，解决了高性能FPGA中收发器工艺节点依赖和集成密度问题。

💡 主要创新点

• 采用嵌入式互连桥（EMIB）实现2.5D封装，将14nm可编程逻辑芯片与20nm收发器芯片高效集成。
• 复用20nm收发器技术，实现收发器路线图的独立性，降低开发成本并提升性能。

🏷 关键词

📄 原文摘要

Kok Hong Chan1, Andy Tong1, Sean Atsatt1, Dana How1, Peter McElheny1, Keith Duwel1, Jeffrey Schulz1, Darren Faulkner3, Gopal Iyer1, George Chen1, Hee Kong Phoon4, Han Wooi Lim4, Wei-Yee Koay4, Ty Garibay3 Intel, San Jose, CA Intel, Toronto, Canada 3 Intel, Austin, TX 4 Intel, Penang, Malaysia 1 2 A Field Programmable Gate Array (FPGA) family was designed to match a programmable fabric die built in 14nm process technology with 28Gb/s transceiver dice. The 2.5D packaging (Fig. 3.3.1) uses embedded interconnect bridges (EMIB) [1]. 20nm transceivers were reused enabling a transceiver roadmap independent of FPGA fabric. Fig. 3.3.2 shows a 560mm2 fabric die and six transceiver dice. The programmable fabric contains 2.8M logic elements, DSP, memory components, and routing interconnect operating at up to 1GHz. Applications drove the need for improved flexibility and security of the FPGA configuration system. A triple-modular redundant microprocessor-based secure

👥 作者与机构

David Greenhill1, Ron Ho1, David Lewis2, Herman Schmit1,