← 返回论文列表 📄 下载原文 PDF  ISSCC 2017 · 20.6
ISSCC 2017Session 20 · DIGITAL VOLTAGE REGULATORS AND LOW-POWER TECHNIQUESDigital Circuits

A 0.5V-VIN 1.44mA-Class Event-Driven Digital LDO with a Fully Integrated 100pF Output Capacitor

⚡ 本页包含 AI 生成的分析内容,仅供参考

📋 论文概要

本文提出了一种基于事件驱动控制的数字低压差稳压器(LDO),实现了完全集成的100pF输出电容,在0.5V输入电压下提供1.44mA级别的负载电流。该设计通过事件驱动方案大幅降低了输出电容需求,避免了传统高频数字LDO的功率效率问题。

💡 主要创新点

重要性
发表年份
ISSCC 2017

🏷 关键词

数字LDO事件驱动控制低输入电压片上输出电容低功耗设计

📄 原文摘要

SK hynix, Icheon, Korea 1 2 In today’s system-on-chip designs, a low-drop-out voltage regulator (LDO) is one of the most popular choices to create a distinct voltage domain owing to its high power density. Many LDOs, however, need a large output capacitor (COUT) to compensate a fast load current (ILOAD) change, increasing the number of pins and off-chip components. In synchronous digital LDO designs, high frequency can miniaturize COUT, but it inevitably causes power inefficiency [2]. A recent work has instead employed an event-driven (ED) control scheme to alleviate the COUT requirement, demonstrating a 400μA-class digital LDO with a COUT of 400pF [1]. The ED scheme is promising, but it is still desirable to develop an LDO which can support a larger ILOAD with a smaller COUT. This is indeed a daunting challenge since a substantial reduction in feedback latency (TLAT) is necessary to retain the same

👥 作者与机构

Doyun Kim1, Jonghwan Kim2, Hyunju Ham2, Mingoo Seok1

Columbia University, New York, NY

分类:Digital Circuits · 年份:ISSCC 2017