A 56Gb/s PAM-4/NRZ Transceiver in 40nm CMOS

📋 论文概要

本文提出了一款采用40nm CMOS工艺的56Gb/s PAM-4/NRZ收发器，集成了串化/解串器、FFE/CTLE/DFE均衡、CDR和眼图监测电路，解决了超高速数据链路（如400GbE）中高性能与低功耗的挑战。该收发器在14GHz下24dB损耗时实现BER<10^-12，功耗仅602mW。

💡 主要创新点

• 采用高度并行化架构，集成64:4串化器和3抽头四分之一速率FFE，实现56Gb/s高速传输。
• 通过多相滤波器（PPF）产生正交时钟，优化锁存器和选择器的时序，降低功耗并提升信号完整性。

🏷 关键词

📄 原文摘要

Ultra-high speed data links such as 400GbE continuously push transceivers to achieve better performance and lower power consumption. This paper presents a highly parallelized TRX at 56Gb/s with integrated serializer/deserializer, FFE/CTLE/DFE, CDR, and eye-monitoring circuits. It achieves BER<10–12 under 24dB loss at 14GHz while dissipating 602mW of power. Figure 6.1.1(a) illustrates the TX structure, which consists of a 64:4 serializer, a 3-tap quarter-rate FFE, a poly-phase filter (PPF) generating quadrature clocks for the latches and selectors, and a combiner (output driver). The low-speed 64:4 serializer can be done in typical CMOS (digital) realization. The 4×14Gb/s inputs coming from it are fed into the quarter-rate FFE, which provides maximum boost of approximately 8dB at 14GHz (Nyquist frequency). Owing to the quarter-rate operation, most of the circuits are realized in CMOS (digital) format, saving

👥 作者与机构

Pen-Jui Peng, Jeng-Feng Li, Li-Yang Chen, Jri Lee

National Taiwan University, Taipei, Taiwan